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Controlled tapered angle etching process for fabricating optical integrated circuits

  • US 5,473,710 A
  • Filed: 10/08/1993
  • Issued: 12/05/1995
  • Est. Priority Date: 10/08/1993
  • Status: Expired due to Term
First Claim
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1. A system for fabricating an OIC device with specific optical coupling efficiency requirement comprising:

  • a tapered angle computing means for receiving said optical coupling efficiency requirement (T) to compute a required tapered angle θ

    according to an equation;

    
    
    space="preserve" listing-type="equation">θ

    =R.sup.-1 (T) where R-1 is a reverse transforming function derived from a set of electromagnetic wave transportation equations;

    a fabricating controlling means utilizing said required tapered angle and a plurality of functional dependence data of said tapered angle relating to a plurality of fabrication parameters from a database wherein said tapered angle θ

    being represented as a function of an etching time (Et), an etching temperature, (Etemp), a concentration of the etchant solution (C), a photoresist material (M), and a photoresist thickness (D) as;

    
    
    space="preserve" listing-type="equation">θ

    =F(E.sub.t, E.sub.temp, C, M, D) said etching means performs an etching process on an OIC chip which includes a semiconductor substrate having a top surface, a buffer layer formed on said top surface and a photoresist layer formed on top of said buffer layer defining an etching window; and

    said buffer layer being a silicon dioxide layer, said photoresist layer is a positive photoresist layer having thickness approximately 2.1 μ

    m or greater, said etchant is a mixture of two etchants NH4F(40%) and HF(40%) at ratio of approximately 30;

    1, said etching temperature is controlled at an approximate range from 22.5°

    to 57°

    C. for an etching time of approximately nine to sixty minutes for making a tapered angle of ranging approximately from 7°

    to 12°

    .

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