System having input output pins shifting between programming mode and normal mode to program memory without dedicating input output pins for programming mode

• US 5,473,758 A
• Filed: 08/31/1992
• Issued: 12/05/1995
• Est. Priority Date: 08/31/1992
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Mitra, Sumit, Drake, Rodney, Allen, Ray
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Meky, Moustafa M.
• Application Number:
  US07/938,911
• Time in Patent Office: 1,191 Days
• Field of Search: 395/275, 395/375, 395/500, 395/425, 395/800, 364/232.8, 364/232.9, 364/221.6, 364/244.6, 364/946.2, 364/946.9, 364/949.2, 364/965.76, 364/716, 307/465, 307/449, 307/450, 307/468, 365/52
• US Class Current: 711/103
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.

Claims

1. A device implemented to be programmed in accordance with instruction words entered as digital bits after installation of the device in circuit with a system to be controlled by the device, comprising:

a microcontroller for controlling the system,

a programmable memory for the microcontroller,

means responsive to instruction words entered into the device for programming the memory while the device is installed in circuit with the system to be controlled, including means for enabling suppression of perturbations of the system which would otherwise occur during in-circuit programming so as to avoid effects on system operation while the programming is taking place;

a plurality of input/output (I/O) pins for receiving data including instruction words to be entered into the device, the number of I/O pins being smaller than the number of bits in an instruction word wherein at least some of said I/O pins are dual function and are shifted between a programming mode and a normal mode; and

mode selection means associated with said at least some of the I/O pins but less than all of the I/O pins, for selectively enabling said at least some of the I/O pins to additionally function to receive data serially when in said programming mode for purposes of programming the memory while the other I/O pins are adapted to receive data in parallel thereby eliminating the need for dedicated programming I/O pins.

2. The device of claim 1, wherein:

the suppression enabling means includes impedance means for isolating the system and its operation from the instruction words being entered into the device.

3. The device of claim 1, wherein:

the programming means includes a data latch for receiving and retaining digital data including instruction words entered into the latch in either serial fashion or parallel fashion, or in a combination of both.

4. The device of claim 3, wherein:

the data latch has a bit capacity consistent with the width of instruction words and greater than the number of said plurality of input/output pins.

5. The device of claim 4, further including:

means for entering data received on the input/output pins into the data latch either serially or in parallel or both, to accommodate all of the bits in an instruction word despite the smaller number of input/output pins.

6. The device of claim 5, further including:

intermediate data storage means coupled between the input/output pins and the data latch for temporarily holding data to be entered into the data latch.

7. The device of claim 1, wherein:

the programmable memory is an EPROM.

8. A programmable semiconductor microcontroller chip for installing into and to control an electrically operated system, comprising:

a plurality of input/output (I/O) pins for receiving instruction words and data entered in the form of electrical signals to be processed by the microcontroller chip, the total number of said I/O pins is less than the number of bits in an instruction word,

an on-chip programmable memory adapted to be programmed by instruction words received as inputs to the microcontroller chip at the (I/O) pins, means for selectively implementing electrical isolation of at least some of the I/O pins from the system to be controlled by the microcontroller chip, to suppress disturbances to the system when the memory is being programmed with the microcontroller chip installed in the system; and

interface means for selectively responding to instruction words entered via at least some of said I/O pins in either serial or parallel fashion to program the programmable memory wherein said at least some of said I/O pins are dual function for shifting the chip between a programming mode and a normal mode, such that during said programming mode said at least some of said I/O pins are used to program said on-chip programming memory and during said normal mode said at least some of said I/O pins are used for inputting and outputting data appropriate for implementing control of the system in which the microcontroller chip is installed, thereby eliminating the need for dedicated programming I/O pins.

9. The invention of claim 8, wherein:

the programmable memory is an EPROM.

10. A method of programming a programmable microcontroller for installing into and for controlling an electrically operated system, while the microcontroller is installed within the system, the microcontroller having a plurality of input ports, the method comprising the steps of:

selecting at least some of the input ports for performing a dual function according to whether the microcontroller is operating in a normal mode or a programming mode and thereby eliminating the need for dedicated programming pins,

using said at least some of the input ports for receiving instruction words to be entered in the microcontroller while in said normal mode, the number of input ports being smaller than the number of bits in an instruction word

using said at least some of the input ports for receiving data serially to be used to program the microcontroller while in said program mode; and

,

substantially isolating electrical levels associated with programming the microcontroller from the circuit of the system to be controlled, with the microcontroller installed in circuit with the system, to preclude disturbances to the system during the in-system programming.