Process of mounting tape automated bonded semiconductor chip on printed circuit board through bumps

• US 5,474,957 A
• Filed: 04/28/1995
• Issued: 12/12/1995
• Est. Priority Date: 05/09/1994
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Urushima, Michitaka
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/430,590
• Time in Patent Office: 228 Days
• Field of Search: 437/209, 437/210, 437/211, 437/212, 437/213, 437/214, 437/215, 437/216, 437/217, 437/218, 437/219, 437/220
• US Class Current: 29/827
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 2201/10681 Tape Carrier Package [TCP]; Flexible sheet connector
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

Conductive leads are connected at inner ends thereof to electrodes of a semiconductor chip through a tape automated bonding process, and bumps are formed on the other ends of the conductive leads so as to economically and reliably mount the semiconductor chip on a circuit board through a concurrent reflow.

Claims

1. A process of mounting a semiconductor chip on a conductive circuit pattern, comprising the steps of:

a) preparing a tape automated bonding tape having a film carrier tape formed with sprocket holes, a device hole and separation holes around said device hole and a pattern formed from a metal film on one surface of said film carrier tape and containing inner leads and pads coplanar with said inner leads;

b) connecting said inner leads to electrodes of a semiconductor chip;

c) covering connections between said inner leads and said electrodes with a piece of resin for protecting said semiconductor chip and making said connection secure;

d) forming bumps on said pads;

cutting along said separation holes for a separation;

e) aligning said bumps with pads formed on a mounting board; and

f) connecting said bumps to said pads on said mounting board.

2. A process of mounting a semiconductor chip on a mounting board means, comprising the steps of:

a) preparing a semiconductor chip, a mounting board means and a tape-automated bonding tape including a film carrier tape having a first area and a second area separable from said first area and a conductive pattern having inner leads and pads electrically connected to said inner leads formed in said second area;

b) bonding said inner leads to electrodes of said semiconductor chip;

c) forming conductive bumps on said pads;

d) separating said second area having said conductive pattern electrically connected to said electrodes of said semiconductor chip from said first area; and

e) bonding said conductive bumps to a conductive pattern on said mounting board means.

3. The process as set forth in claim 2, further comprising the step of coating said conductive pattern and an exposed sub-area of said second area with a cover-resist layer having holes exposing at least central areas of said pads between said step a) and said step b).

4. The process as set forth in claim 3, in which said cover-resist layer has an initial elastic modulus not greater than a tenth of an elastic modulus of said film carrier tape.

5. The process as set forth in claim 2, further comprising the step of supplying a piece of resin to said semiconductor chip and a part of said film carrier tape for preventing said electrodes and said inner leads from contamination and securely fixing said semiconductor chip to said film carrier tape.

6. The process as set forth in claim 2, in which said conductive bumps bonds said pads to said conductive pattern of said board means through a reflow.

7. The process as set forth in claim 6, in which said reflow is carried out in an inert atmosphere.

8. The process as set forth in claim 2, in which said tape-automated bonding tape further includes a suspended lead extending over a space where said semiconductor chip occupies at said step b),

said process further comprising the step of coating said conductive pattern and an exposed sub-area of said second area with a cover-resist layer having holes exposing at least central areas of said pads and an area of said suspended lead between said step a) and said step b).

a heat radiating bump being further formed on the area of said suspended lead.

9. The process as set forth in claim 2, further comprising the step of attaching a heat radiating plate to said semiconductor chip.

10. The process as set forth in claim 9, further comprising the step of attaching a heat sink to said heat radiating plate.

11. The process as set forth in claim 8, further comprising the step of attaching a heat radiating plate to said semiconductor chip after said step e).

12. The process as set forth in claim 11, further comprising the step of attaching a heat sink to said heat radiating plate.

13. The process as set forth in claim 2, in which said inner leads are concurrently bonded to said electrodes.

14. The process as set forth in claim 2, in which said inner leads are sequentially bonded to said electrodes.