Method for making semiconductor device having no die supporting surface

• US 5,474,958 A
• Filed: 05/04/1993
• Issued: 12/12/1995
• Est. Priority Date: 05/04/1993
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Postlethwait, Les, Pastore, John R., Nomi, Victor K., Reeves, Twila J., Djennas, Frank
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Pham, Long
• Application Number:
  US08/055,863
• Time in Patent Office: 952 Days
• Field of Search: 437/211, 437/212, 437/215, 437/217, 437/220, 437/209, 257/676, 257/787
• US Class Current: 29/827
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78743 Suction holding means
• CPC Class Codes: H01L 2224/78744 in the lower part of the bonding apparatus, e.g. in the apparatus chuck
• CPC Class Codes: H01L 2224/85001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49172 : by molding of insulating material

Abstract

A wire bondable plastic encapsulated semiconductor device (58) having no die supporting surface can be manufactured. In one embodiment, a semiconductor die (22) and a plurality of conductors (12) extending toward the periphery of the die are provided. The die is rigidly held in place on a workholder (60) with a vacuum (62) for the wire bonding process. Wire bonds (26) electrically connect the die to the conductors. The wire bonded die is then placed inside a mold cavity (64), and a resin encapsulated is transferred into the cavity under elevated temperature and pressure to form package body (70) around the die, the wire bonds and a portion of the conductors. Before the package body is formed, the die is supported solely by the the rigidity of the wire bonds since there is no die supporting surface connected to the conductors.

Claims

1. A method for fabricating a semiconductor device comprising the steps of:

placing a semiconductor die having an active surface and a periphery on a supporting workholder;

attaching an inactive surface of the semiconductor die to a removable tape, the tape being supported by the workholder to rigidly hold the semiconductor die in a fixed position on the workholder;

providing a first plurality of conductors extending toward the periphery of the semiconductor die;

wire bonding the active surface of the semiconductor die to the first plurality of conductors;

forming a package body, having planar surfaces, to cover the active surface of the semiconductor die and a portion of the plurality of conductors; and

providing a second plurality of conductors electrically connected to the semiconductor die to provide external electrical connections.

11. The method of claim 1, wherein the step of providing the first plurality of conductors comprises providing a PCB substrate having a die cavity and a plurality of conductive traces on a surface of the PCB substrate.

12. The method of claim 11, wherein the step of providing a PCB substrate comprises providing a PCB substrate having a die cavity having a plated sidewall, wherein the plated sidewall is connected to a power supply trace.

13. The method of claim 11, wherein the step of providing a PCB substrate comprises providing a PCB substrate having a plurality of recesses on a surface, the plurality of recesses corresponding in location to a plurality of solder pads which is electrically connected to the plurality of conductive traces.

2. A method for fabricating a semiconductor device comprising the steps of:

placing a semiconductor die having an active surface and a periphery on a supporting workholder;

providing means for holding the semiconductor die rigidly on the supporting workholder for a subsequent electrical connecting step;

providing a first plurality of conductors extending toward the periphery of the semiconductor die;

electrically connecting the active surface of the semiconductor die to the first plurality of conductors;

supporting an inactive surface of the semiconductor die with a support pin in a mold;

molding a resin encapsulant inside a mold cavity having planar major surfaces to form a package body to cover the active surface of the semiconductor die and a portion of the plurality of conductors; and

providing a second plurality of conductors electrically connected to the semiconductor die to provide external electrical connections.

3. The method of claim 2, wherein the step of supporting further comprises providing a vacuum line around the support pin.

4. A method for fabricating a semiconductor device comprising the steps of:

placing a semiconductor die having an active surface and a periphery on a supporting workholder;

providing means for holding the semiconductor die rigidly on the supporting workholder for a subsequent electrical connecting step;

providing a first plurality of conductors extending toward the periphery of the semiconductor die;

electrically connecting the active surface of the semiconductor die to the first plurality of conductors with connecting means, wherein said connecting means holds in place and physically supports the semiconductor die;

supporting an inactive surface of the semiconductor die with a surface of a mold platen which defines part of a mold cavity;

activating a vacuum line to rigidly hold the inactive surface against the mold platen surface; and

transferring a resin encapsulant inside the mold cavity having planar major surfaces to form a package body to cover the active surface of the semiconductor die and a portion of the plurality of conductors; and

providing a second plurality of conductors electrically connected to the semiconductor die to provide external electrical connections.

5. The method of claim 4, further comprising the step of:

attaching a heat sink to the inactive surface of the semiconductor die after the step of molding.

8. The method of claim 4, wherein the step of electrically connecting comprises a method selected from a group consisting of;

wire bonding and low loop wire bonding.

9. The method of claim 4, further comprising the step of:

heating the supporting workholder to a temperature in a range of 175°

C. to 250°

C.

10. The method of claim 4, wherein the steps of providing the first and second pluralities of conductors comprise providing a flagless leadframe.

6. A method for fabricating a semiconductor device comprising the steps of:

placing a semiconductor die having an active surface and a periphery on a supporting workholder;

providing means for holding the semiconductor die rigidly on the supporting workholder for a subsequent electrical connecting step;

providing a first plurality of conductors extending toward the periphery of the semiconductor die;

electrically connecting the active surface of the semiconductor die to the first plurality of conductors;

supporting a portion of an inactive surface of the semiconductor die with a pedestal which extends into a mold cavity;

molding a resin encapsulant inside the mold cavity having planar major surfaces to form a package body to cover the active surface of the semiconductor die and a portion of the plurality of conductors; and

providing a second plurality of conductors electrically connected to the semiconductor die to provide external electrical connections.

7. The method of claim 6, further comprising the step of:

attaching a heat sink to the portion of the inactive surface of the semiconductor die after the step of molding.

14. A method for fabricating a semiconductor device comprising the steps of:

placing a semiconductor die having an active surface and a periphery on a supporting workholder;

providing means for holding the semiconductor die rigidly on the supporting workholder for a subsequent electrical connecting step;

providing a PCB substrate having a die cavity and a plurality of conductive traces on a surface of the PCB substrate, the plurality of conductive traces extending toward the periphery of the semiconductor die;

electrically connecting the active surface of the semiconductor die to the first plurality of conductors;

providing a removable tape that adheres to an inactive surface of the semiconductor die;

forming a package body to cover the active surface of the semiconductor die and a portion of the plurality of conductive traces;

removing a first portion of the tape from the inactive surface of the semiconductor die after the step of forming a package body, such that a second portion of the tape remains on the inactive surface forming a plurality of solder resist annular rings on the inactive surface;

attaching a first plurality of solder balls to the inactive surface of the semiconductor die inside the plurality of solder resist annular rings; and

attaching a second plurality of solder balls to the plurality of solder pads inside the plurality of recesses in the multilayer PCB substrate.