Asynchronous digital sample rate converter
First Claim
1. A system for converting a sequence of input samples at a first sampling rate to a sequence of output samples at a second sampling rate, the system comprising:
- means for producing a periodically overflowing ramp signal at the second sampling rate having an average slope proportional to the first sampling rate, an integer part and a fractional part; and
a first memory element for storing the input samples received at the first sampling rate;
a second memory element for storing coefficients;
means for selecting and accessing input samples from the first memory element according to the integer part of the ramp signal and an increment value related to the first and second sampling rates;
means for selecting and accessing coefficients from the second memory element according to the fractional part of the ramp signal and an increment value related to the first and second sampling rates;
means for computing filter coefficients according to both the fractional part of the ramp signal and the selected coefficients; and
means for producing, at the second sampling rate, an output sample as a sum of products of the selected input samples and computed filter coefficients.
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Accused Products
Abstract
An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.
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Citations
57 Claims
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1. A system for converting a sequence of input samples at a first sampling rate to a sequence of output samples at a second sampling rate, the system comprising:
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means for producing a periodically overflowing ramp signal at the second sampling rate having an average slope proportional to the first sampling rate, an integer part and a fractional part; and a first memory element for storing the input samples received at the first sampling rate; a second memory element for storing coefficients; means for selecting and accessing input samples from the first memory element according to the integer part of the ramp signal and an increment value related to the first and second sampling rates; means for selecting and accessing coefficients from the second memory element according to the fractional part of the ramp signal and an increment value related to the first and second sampling rates; means for computing filter coefficients according to both the fractional part of the ramp signal and the selected coefficients; and means for producing, at the second sampling rate, an output sample as a sum of products of the selected input samples and computed filter coefficients. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A system for converting a sequence of input samples at a first sampling rate defining an input period to a sequence of output samples at a second sampling rate, comprising:
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a coefficient memory in which a set of filter coefficients is stored; means for measuring a time period between an arrival of an input sample and an immediately subsequent output sample request, comprising means for receiving a clock signal providing pulses occurring at a rate independent of and substantially higher than the first and second sampling rates, and means for counting a number of pulses of the received clock signal occurring between the arrival of the input sample and the arrival of the immediately subsequent output sample request; and means for selecting, at the second sampling rate, a plurality of filter coefficients from the coefficient memory according to a first coefficient address, defined by a ratio of the measured time period to the input period, and an increment value related to the first and second sampling rates; and means for computing an output sample as a sum of products of the sequence of input samples and the selected filter coefficients. - View Dependent Claims (22)
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23. A system for convening a first sequence of input samples at a first sampling rate to a second sequence of output samples m a second sampling rate, comprising:
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means for generating a first coefficient address related to the first and second sampling rates and a phase difference between the first sequence and the second sequence; means for storing a predetermined set of filter coefficients, means, responsive to the input and output sample rates, for determining a scaling value according to a ratio of the second sampling rate to the first sampling rate; and means for determining a sum of products of the first sequence input samples and selected filter coefficients, including means for scaling the first coefficient address by the scaling value, and means for accessing and selecting the filter coefficients according to the scaled first coefficient address and the scaling value. - View Dependent Claims (24, 25, 26, 27)
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28. A digital integrated circuit for convening a sequence of input samples arriving at a first sampling rate defining an input period to a sequence of output samples at a second sampling rate and having an input for receiving a master clock signal from an external signal source, the master clock signal having a frequency independent of and substantially higher than the first and second sampling rates, and comprising:
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means, clocked by the master clock signal, for determining a measure of a time period between an arrival of an input sample and an arrival of an immediately subsequent request for an output sample; means for storing a set of predetermined filter coefficients; means for selecting some of the predetermined filter coefficients according to a ratio of the measure of the time period to the input period and a ratio between the first and second sampling rates; and means for computing an output sample from the sequence of input samples and the selected filter coefficients.
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29. A method for converting a sequence of input samples at a first sampling rate to a sequence of output samples at a second sampling rate, comprising the steps of:
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storing input samples in a first memory element at the first sampling rate; generating a periodically overflowing ramp signal at the second sampling rate with an average slope proportional to the first sampling rate and having an integer part and a fractional part and an increment value related to the first and second sampling rates; selecting, in response to an output sample request, input samples stored in the first memory element according to the integer part of the ramp signal and an increment value related to the first and second sampling rates; selecting, in response to an output sample request, coefficients stored in a second memory element according to the fractional part; computing filter coefficients according to the fractional part of the ramp signal and the selected coefficients; and producing, in response to an output sample request, an output sample as a sum of products of the selected input samples and the computer filter coefficients. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. A method for converting a sequence of input samples at a first sampling rate defining an input period to a sequence of output samples at a second sampling rate, using a set of filter coefficients stored in a memory comprising the steps of:
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measuring a time period between an arrival of an input sample and an immediately subsequent output sample request by receiving a signal having pulses occurring at a rate independent of and substantially higher than the first and second sampling rates and counting the pulses of the received clock signal occurring between an arrival of an input sample and an arrival of an immediately subsequent output sample request; selecting a plurality of filter coefficients according to a first coefficient address defined by a ratio between the measure of the time period and the input period, and an increment value related to the first and second sampling rates; and computing an output sample as a sum of products of the selected filter coefficients and the sequence of input samples. - View Dependent Claims (51)
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52. A method for converting a first sequence of input samples at a first sampling rate to a second sequence of output samples at a second sampling rate using a set of filter coefficients stored in a memory, given a first coefficient address related to the first and second sampling rates comprising the steps of:
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generating a first coefficient address related to the first and second sampling rates and a phase difference between the first sequence and the second sequence; determining a scaling value according to a ratio of the second sampling rate 19 the first sampling rate; and computing, in response to an output sample request, such output sample requests occurring at the second sampling rate, a sum of products of the first sequence of input samples and selected filter coefficients, including scaling the first coefficient address by the scaling value to obtain an address to select a first filter coefficient from the memory, and accessing grid selecting the filter coefficients from the memory according to the scaled first coefficient address and the scaling value. - View Dependent Claims (53, 54, 55, 56)
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57. A method for convening a sequence of input samples arriving at a first sampling rate defining in input period to a sequence of output samples at a second sampling rate, using a set of filter coefficients stored in a memory, comprising the steps of:
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receiving a clock signal comprised of pulses occurring at a rate independent of and substantially higher than the first and second sampling rates; counting a number of pulses occurring between an arrival of an input sample and an arrival of an immediately subsequent request for an output sample; selecting and accessing some of the filter coefficients from the memory according to a ratio between the number of pulses counted and the input period and a ratio between the first and second sampling rates; and producing an output sample as a sum of products of the sequence of input samples and the selected filter coefficients.
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Specification