Dynamic random access memory with bit line preamp/driver

• US 5,475,642 A
• Filed: 06/23/1992
• Issued: 12/12/1995
• Est. Priority Date: 06/23/1992
• Status: Expired due to Fees

• Current Assignee: David L. Taylor
• Original Assignee: David L. Taylor
• Inventors: Taylor, David L.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): DINH, SON T
• Application Number:
  US07/902,387
• Time in Patent Office: 1,267 Days
• Field of Search: 365/149, 365/190, 365/203, 365/205
• US Class Current: 365/203
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

A preamp/driver circuit (18) is disclosed which is operable to interface a Bit Line (14) with a Data Line (20). The Bit Line (14) has a plurality of memory cells associated therewith which are selectable by Word Lines. The preamp/driver (18) decouples the Bit Line (14) from the Data Line (20) and drives Data Line (20) from a separate source. The preamp/driver (18) is comprised of a depletion transistor (22) that has the gate thereof connected to the Bit Line (14) and drives a source follower (26). The source follower (26) drives the Data Line (20) from the supply potential. The system is operable during a restore operation to write back to the Bit Line (14) from the Data Line (20) through a Write transistor (28). The restore operation is effected with a restore amplifier with the Read operation effected through a separate sensing device that converts the voltage on the Data Lines to full logic potentials.

Claims

1. A random access memory, comprising:

a plurality of single transistor memory cells configured in an array and each having a memory capacitor for storing a logic "0" voltage or a logic "1" voltage;

an inner Bit Line;

an access device for selectively connecting one of said memory cells to said inner Bit Line in response to an external access signal such that said memory capacitor can transfer charge to and from said inner Bit Line;

an outer Bit Line;

a Bit Line preamp/driver circuit for driving said outer Bit Line from a source different from said inner Bit Line as said access device accesses said memory cell, such that said outer Bit Line is not directly coupled to said inner Bit Line, said outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in said accessed memory cell; and

a restore circuit interfaced with said outer Bit Line and operable to sense the logic state on said outer Bit Line and drive the voltage on said outer Bit Line to either a full logic voltage or to a ground voltage, respectively, during a restore operation depending upon whether said logic "1" voltage as said logic "0" voltage is present on said outer Bit Line, said restore circuit operable to drive said inner Bit Line to substantially the same voltage as the outer Bit Line during said restore operation.

2. The memory of claim 1 and further comprising a read circuit for distinguishing between a logic "0" and a logic "1" voltage on said outer Bit Line and converting the voltage on said outer Bit Line to a substantially amplified voltage in response to the logic state determined to be on said outer Bit Line.

3. The memory of claim 1, wherein said restore circuit comprises:

a cross-coupled latch having first and second sense nodes, with one of said first and second sense nodes connected to a reference voltage and the other of said first and second sense nodes connected to said outer Bit Line, said latch operable to distinguish between a logic "1" voltage and a logic "0" voltage on said outer Bit Line and operable to drive said outer Bit Line to substantially full logic levels as a function of the distinguished logic voltage thereon;

a Write device for selectively connecting said outer Bit Line to said inner Bit Line to drive said inner Bit Line from said outer Bit Line; and

a Restore control signal to activate said Write device during a restore operation after said access device has selectively connected one of said memory cells to said inner Bit Line.

4. The memory of claim 1, and further comprising:

a Data Line for being disposed at a logic "1" voltage or a logic "0" voltage;

an interface device for driving said Data Line from a source other than said inner Bit Line or said outer Bit Line, said interface device isolated from said outer Bit Line by said Bit Line preamp/driver circuit;

said interface device controlled by the logic voltage on said inner Bit Line such that the logic voltage on said Data Line corresponds to the logic voltage on said inner Bit Line; and

a Read circuit for distinguishing between a logic "0" and a logic "1" voltage on said Data Line and driving said Data Line to either a full circuit potential or to ground in response to the logic state determined to be on said Data Line.

5. The memory of claim 4 wherein said interface device comprises:

a depletion transistor configured as a source follower having the source/drain path thereof disposed between a source other than said outer or inner Bit Line and said Data Line; and

a current source for being driven by said depletion transistor, the gate of said depletion transistor controlled by the voltage on said inner Bit Line.

6. The memory of claim 1 and further comprising:

a Data Line for being disposed at either a logic "1" voltage or a logic "0" voltage;

an interface device for driving said Data Line from a source other than said outer Bit Line or said inner Bit Line;

said interface device controlled by the logic voltage on said outer Bit Line such that the logic voltage on said Data Line corresponds to the logic voltage on said outer Bit Line; and

a Read circuit for distinguishing between a logic "0" and a logic "1" on said Data Line and driving said Data Line to either a full circuit potential or to ground in response to the logic state determined to be on said Data Line.

7. The memory of claim 6 wherein said interface device comprises:

a depletion transistor configured as a source follower having the source/drain path thereof disposed between a source other than said outer or inner Bit Lines; and

a current source for being driven by said depletion transistor, the gate of said depletion transistor controlled by the voltage on said outer Bit Line.

8. A random access memory, comprising:

a plurality of single transistor memory cells configured in an array and each having a memory capacitor for storing a logic "0" voltage or a logic "1" voltage;

an inner Bit Line;

an access device for selectively connecting one of said memory cells to said inner Bit Line in response to an external access signal such that said memory capacitor can transfer charge to and from said inner Bit Line;

an outer Bit Line;

a Bit Line preamp/driver circuit for driving said outer Bit Line from a source different from said inner Bit Line as said access device accesses said memory cell, such that said outer Bit Line is not directly coupled to said inner Bit Line, said outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in said accessed memory cell; and

a precharge device for precharging said inner Bit Line to a predetermined voltage, said Bit Line preamp/driver circuit operable to shift the voltage on said outer Bit Line to a voltage higher than that on said inner Bit Line for at least one logic state stored in said memory cell.

9. The memory of claim 8, wherein said predetermined voltage is ground.

10. The memory of claim 8, wherein said predetermined voltage is equal to one half of the full supply voltage.

11. The memory of claim 8, wherein said outer Bit Line is precharged to a predetermined voltage.

12. The memory of claim 11, wherein the difference between the voltage on said inner Bit Line and the voltage to which said outer Bit Line is driven by said Bit Line preamp/driver circuit is substantially equal to the voltage to which said outer Bit Line is precharged to.

13. A method for accessing data stored in one of a plurality of single transistor memory cells, each memory cell having a memory capacitor for storing a logic "0" or a logic "1" voltage, comprising the steps of:

providing an inner Bit Line;

accessing one of the single transistor memory cells and connecting the associated memory capacitor to the inner Bit Line such that the memory capacitor can transfer charge to and from the inner Bit Line;

providing an outer Bit Line;

driving the outer Bit Line from a source different than the inner Bit Line as the memory cell is accessed during the step of accessing the memory cell, such that the outer Bit Line is not directly coupled to the inner Bit Line, the outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in the accessed memory cell; and

sensing the logic state on the outer Bit Line during a step of restoring, and driving the voltage on the outer Bit Line to a full logic voltage or to a ground voltage, respectively, during a Restore operation, and substantially concurrently driving the inner Bit Line to the same voltage that is on the outer Bit Line.

14. The method of claim 13, and further comprising distinguishing between a logic "0" and a logic "1" voltage on the outer Bit Line and driving the outer Bit Line to a substantially amplified voltage in response to the logic states determined to be on the outer Bit Line.

15. The method of claim 13, wherein the step of restoring comprises:

providing a cross-coupled latch having first and second sense nodes;

connecting one of the sense nodes to a reference voltage;

connecting the other sense node to the outer Bit Line;

determining whether the voltage on the other sense node is greater than or less than the reference voltage;

driving the sense node connected to the outer Bit Line to a full logic voltage when the voltage on the outer Bit Line is greater than the reference voltage and to a ground voltage when the voltage on the outer Bit Line is lower than the reference voltage, the reference voltage having a value disposed between that existing on the outer Bit Line, substantially midway between a logic "0" and a logic "1" voltage;

selectively connecting the outer Bit Line to the inner Bit Line to drive the inner Bit Line from the outer Bit Line in response to a restore control signal; and

generating the restore control signal to activate the step of selectively connecting during a restore operation after the step of accessing.

16. The method of claim 13, and further comprising:

providing a Data Line separate from the outer Bit Line and having either a logic "1" or a logic "0" voltage disposed thereon;

interfacing the Data Line with the inner Bit Line such that the Data Line is driven from a source other than the outer Bit Line or the inner Bit Line;

controlling the step of interfacing with the voltage on the inner Bit Line such that the logic voltage on the Data Line corresponds to the logic voltage on the inner Bit Line; and

distinguishing between a logic "0" and a logic "1" voltage on the Data Line and convening the voltage on the Data Line to either a full circuit voltage or to a ground voltage in response to the logic state determined to be on the Data Line.

17. The method of claim 16 wherein the step of interfacing comprises:

providing a depletion source follower transistor having a gate and a source/drain path, the source/drain path connected on one side to a supply voltage and other than the inner or outer Bit Lines;

controlling the gate of the source follower with a voltage corresponding to the voltage on the inner Bit Line; and

driving a current source and the Data Line with the other side of the source/drain path of the source follower transistor.

18. The method of claim 13, and further comprising:

providing a Data Line separate from the inner and outer Bit Lines and having a logic "1" or a logic "0" voltage disposed thereon;

interfacing the Data Line with the outer Bit Line such that the Data Line is driven from a source other than the inner Bit Line or the outer Bit Line; and

controlling the step of interfacing with the voltage on the outer Bit Line such that the logic voltage on the Data Line corresponds to the logic voltage on the outer Bit Line;

distinguishing between a logic "0" and a logic "1" voltage on the Data Line and converting the voltage on the Data Line to either a full circuit voltage or to a ground voltage in response to the logic state determined to be on the Data Line.

19. The method of claim 18 wherein the step of interfacing comprises:

providing a depletion source follower transistor having a gate and a source/drain path, the source/drain path connected on one side to a supply voltage other than the outer or inner Bit Lines;

controlling the gate of the source follower with the voltage on the outer bit line; and

driving a current source and the Data Line with the other side of the source/drain path of the source follower transistor.

25. The method of claim 13 wherein the step of driving the outer Bit Line comprises:

providing a depletion device having a negative threshold and connecting the gate thereof to the inner Bit Line;

connecting one side of the source/drain path of the depletion transistor to the gate of an enhancement transistor;

connecting one side of the source/drain path of the depletion transistor to the gate of an enhancement transistor;

connecting one side of the source/drain path of the enhancement transistor to a source voltage and the other side thereof to the outer Bit Line; and

driving the side of the source/drain path thereof opposite to that connected to the gate of the enhancement transistor with a Read control voltage, activation of the Read control voltage operable to drive the outer Bit Line from the inner Bit Line.

20. A method for accessing data stored in one of a plurality of single transistor memory cells, each memory cell having a memory capacitor for storing a logic "0" or a logic "1" voltage, comprising the steps of:

providing an inner Bit Line;

accessing one of the single transistor memory cells and connecting the associated memory capacitor to the inner Bit Line such that the memory capacitor can transfer charge to and from the inner Bit Line;

providing an outer Bit Line;

driving the outer Bit Line from a source different than the inner Bit Line as the memory cell is accessed during the step of accessing the memory cell, such that the outer Bit Line is not directly coupled to the inner Bit Line, the outer Bit Line driven toward either a logic "1" voltage or a logic "0" voltage corresponding to the voltage stored in the accessed memory cell; and

precharging the inner Bit Line to a predetermined voltage, wherein the step of driving the outer Bit Line from a source different from the inner Bit Line comprises shifting the voltage on the outer Bit Line to a voltage higher than that on the inner Bit Line for at least one logic state on the memory cell.

21. The method of claim 20, wherein the step of precharging is operable to precharge the inner Bit Line to substantially ground.

22. The method of claim 20, wherein the step of precharging is operable to precharge the inner Bit Line to a voltage of substantially one half of the full circuit potential.

23. The method of claim 20, and further comprising precharging the outer Bit Line to a predetermined precharge voltage.

24. The method of claim 23, wherein the difference between the voltage to which the outer Bit Line is driven during the step of accessing and the voltage the inner Bit Line for the highest logic potential thereon is substantially equal to the voltage to which the outer Bit Line is precharged.