Screening circuitry for a dynamic random access memory

• US 5,475,646 A
• Filed: 11/16/1994
• Issued: 12/12/1995
• Est. Priority Date: 08/31/1992
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ogihara, Masaki
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/342,000
• Time in Patent Office: 391 Days
• Field of Search: 365/189.09, 365/201, 365/193, 365/222, 365/233, 365/230.03
• US Class Current: 365/222
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode

Abstract

A dynamic random access memory comprising a dynamic memory section, a first screening-test pad, a second screening-test pad, and a mode-setting circuit. The dynamic memory section includes a memory-cell array having dynamic-type memory cells (MC) arranged in rows and columns, a row circuit and a column circuit, both connected to the memory-cell array, and a refresh counter for generating a refresh address signal for refreshing the dynamic-type memory cells when the dynamic memory section is set in a CBR refresh mode. The first screening-test pad receives a first external control signal for setting the dynamic memory section in an ordinary mode or a screening-test mode. The second screening-test pad receives a second external control signal for setting the dynamic memory section in the CBR refresh mode. The mode-setting circuit detects whether or not the first control signal and the second external control signal are in predetermined states, and enables the row circuit and the column circuit upon detecting that the first and second control signals are in the predetermined states, thereby to cause the refresh counter to supply the refresh address signal to the row circuit and the column circuit.

Claims

1. A dynamic random access memory comprising:

a dynamic memory section including a memory-cell array having dynamic-type memory cells (MC) arranged in rows and columns, a row circuit and a column circuit, both connected to said memory-cell array, and a refresh counter for generating a refresh address signal for refreshing said dynamic-type memory cells when said dynamic memory section is set in a CBR (CAS before RAS) refresh mode;

a first screening-test pad for receiving a first external control signal for setting said dynamic memory section in one of an ordinary mode and a screening-test mode;

a second screening-test pad for receiving a second external control signal for setting said dynamic memory section in the CBR refresh mode; and

a mode-setting circuit for detecting whether the first external control signal and the second external control signal are in predetermined states, and for enabling said row circuit and said column circuit upon detecting that the first and second control signals are in the predetermined states, thereby to cause said refresh counter to supply the refresh address signal to said row circuit and said column circuit,

wherein said dynamic memory section further includes;

a power-supply terminal;

a ground terminal;

a plurality of address terminals for receiving an address signal supplied eternally;

a RAS terminal for receiving a RAS (row address strobe) signal supplied eternally;

a CAS terminal for receiving a CAS (column address strobe) signal supplied externally;

a WE terminal for receiving a write enable signal supplied externally;

a data output terminal for outputting data to an external device;

a data input terminal for receiving data to be written eternally;

a row address buffer for receiving a row address signal from one of said address terminals and an output from said refresh counter;

a row decoder for decoding the row address signal supplied from said row address buffer, thereby to select at least one of the rows of memory cells (MC);

a sense amplifier for detecting a potential read from said memory-cell array;

a column to address buffer for receiving a column address signal input from said address terminals;

a column decoder for decoding a column address signal supplied from said column address buffer, thereby to select at least one of the columns of memory cells (MC);

an input/output gate for supplying data to and receiving data from at least one selected column of memory cells (MC), in accordance an output from said column decoder;

a data output buffer for amplifying data read from said input/output gate and outputting the data to said data output terminal;

a data input buffer for amplifying data read from said data input terminal and outputting the data to said data input/output gate;

a control circuit for supplying the output of said refresh counter to said row address buffer when said CAS and RAS signals externally supplied to said CAS terminal and said RAS terminal, respectively, designate a CBR refresh mode, said mode-setting circuit generating a detection signal upon detecting that said first and second control signals are in predetermined states, thereby to enable said memory-cell array, said row address buffer, said row decoder, said sense amplifier, said column address buffer, said column decoder, said input/output gate, and said refresh counter, and supplying the output of said refresh counter to said row address buffer and said column address buffer, thereby to set said dynamic memory section into a screening-test mode, and

a power-supply voltage lowering circuit for lowering a power-supply voltage applied from said power-supply terminal, thereby to generate an internal power-supply voltage, said mode-setting circuit prohibiting said power-supply lowering circuit from lowering the power-supply voltage when said dynamic memory section is set into the screening-test mode.

2. The dynamic random access memory according to claim 1, wherein said mode-setting circuit generates a detection signal upon detecting that the first control signal comes to have a level within a range different from a range in which the first control signal is used, after said dynamic memory section has been set into a screening-test mode, thereby to set said dynamic memory section into a write mode.

3. The dynamic random access memory according to claim 1, wherein said mode-setting circuit generates a detection signal upon detecting that the first control signal changes in level after said dynamic memory section has been set into a screening-test mode, thereby to set said dynamic memory section into a write mode.

4. The dynamic random access memory according to claim 2, wherein said mode-setting circuit controls said dynamic memory section such that said dynamic memory section receives the most significant bit output from said refresh counter as input data, while being set in the write mode.

5. The dynamic random access memory according to claim 3, wherein said mode-setting circuit controls said dynamic memory section such that said dynamic memory section receives the most significant bit output from said refresh counter as input data, while being set in the write mode.

6. The dynamic random access memory according to claim 2, wherein said mode-setting circuit controls said dynamic memory section such that said dynamic memory section receives, as input data, data obtained by inverting data supplied from said input/output gate, while being set in the write mode.

7. The dynamic random access memory according to claim 3, wherein said mode-setting circuit controls said dynamic memory section such that said dynamic memory section receives, as input data, data obtained by inverting data supplied from said input/output gate, while being set in the write mode.

10. The dynamic random access memory according to any one of claims 1 to 7, wherein said dynamic memory section further has an address switch circuit connected between an output node of said row address buffer and said address terminals, and said mode-setting circuit turns on said address switch circuit, thereby to set said dynamic memory section into the screening-test mode.

8. A dynamic random access memory comprising:

a dynamic memory section including a memory-cell array having dynamic-type memory cells (MC) arranged in rows and columns, a row circuit and a column circuit, both connected to said memory-cell array, and a refresh counter for generating a refresh address signal for refreshing said dynamic-type memory cells when said dynamic memory section is set in a CBR (CAS before RAS) refresh mode;

a power-supply terminal;

a first screening-test pad for receiving a first external control signal for setting said dynamic memory section in an ordinary mode or a screening-test mode;

a second screening-test pad for receiving a second external control signal for setting said dynamic memory section in the CBR refresh mode; and

a mode-setting circuit for detecting whether the first external control signal and the second external control signal are in predetermined states, for setting said dynamic memory section into a screening-test mode upon detecting that the first and second external control signals are in the predetermined states, and for enabling said row circuit and said column circuit upon detecting that the first and second external control signals are in the predetermined states, thereby to cause said refresh counter to supply the refresh address signal to said row circuit and the column circuit,

wherein said dynamic memory section further has a power-supply voltage lowering circuit for lowering a power-supply voltage applied from said power-supply terminal, thereby to generate an internal power-supply voltage, and said mode-setting circuit prohibits said power-supply lowering circuit from lowering the power-supply voltage when said dynamic memory section is set into the screening-test mode.

9. The dynamic random access memory according to claim 8, wherein said dynamic memory section further has a voltage raising circuit for raising an internal power-supply voltage, thereby to generate a word-line driving voltage to be applied to said row decoder, and said mode-setting circuit prohibits said voltage raising circuit from raising the power-supply voltage, thereby to set the word-line driving voltage at the internal power-supply voltage, when said dynamic memory section is set into the screening-test mode.

11. The dynamic random access memory according to claim 8, wherein:

said dynamic memory section further has a plurality of address terminals for receiving an address signal supplied eternally, a row address buffer for receiving a row address signal from said address terminals or an output from said refresh counter and an address switch circuit connected between an output node of said row address buffer and said address terminals; and

said mode-setting circuit turns on said address switch circuit, thereby to set said dynamic memory section into the screening-test mode.

12. The dynamic random access memory according to claim 9, wherein:

said dynamic memory section further has a plurality of address terminals for receiving an address signal supplied externally, a row address buffer for receiving a row address signal from said address terminals or an output from said refresh counter and an address switch circuit connected between an output node of said row address buffer and said address terminals; and

said mode-setting circuit turns on said address switch circuit, thereby to set said dynamic memory section into the screening-test mode.

13. A dynamic random access memory comprising:

a dynamic memory section including a memory-cell array having dynamic-type memory cells (MC) arranged in rows and columns, a row circuit and a column circuit, both connected to said memory-cell array, and a refresh counter for generating a refresh address signal for refreshing said dynamic-type memory cells when said dynamic memory section is set in a CBR (CAS before RAS) refresh mode;

a first screening-test pad for receiving a first external control signal for setting said dynamic memory section in an ordinary mode or a screening-test mode;

a second screening-test pad for receiving a second external control signal for setting said dynamic memory section in the CBR refresh mode;

a mode-setting circuit for detecting whether the first external control signal and the second external control signals are in predetermined states, for setting said dynamic memory section into a screening-test mode upon detecting that the first and second external control signals are in the predetermined states, and for enabling said row circuit and column circuit upon detecting that the first and second external control signals are in the predetermined states, thereby to cause said refresh counter to supply the refresh address signal to said row circuit and said column circuit,

wherein said dynamic memory section further includes;

a power-supply terminal;

a ground terminal;

a plurality of address terminals for receiving an address signal supplied externally;

a RAS terminal for receiving a RAS (row address strobe) signal supplied externally;

a CAS terminal for receiving a CAS (column address strobe) signal supplied externally;

a WE terminal for receiving a write enable signal supplied eternally;

a data output terminal for outputting data to an external device;

a data input terminal for receiving data to be written externally;

a row address buffer for receiving a row address signal from one of said address terminals and an output from said refresh counter;

a row decoder for decoding the row address signal supplied from said row address buffer, thereby to select at least one of the rows of memory cells (MC);

a sense amplifier for detecting a potential read from said memory-cell array;

a column address buffer for receiving a column address signal input from said address terminals;

a column decoder for decoding a column address signal supplied from said column address buffer, thereby to select at least one of the columns of memory cells (MC);

an input/output gate for supplying data to and receiving data from at least one selected column of memory cells (MC), in accordance with an output from said column decoder;

a data output buffer for amplifying data read from said input/output gate and outputting the data to said data output terminal;

a data input buffer for amplifying data read from said data input terminal and outputting the data to said data input/output gate;

a control circuit for supplying the output of said refresh counter to said row address buffer when said CAS and RAS signals externally supplied to said CAS terminal and said RAS terminal, respectively, designate a CBR refresh mode; and

an address switch circuit connected between the output said row address buffer and said address terminals, said mode-setting circuit generating a detection signal upon detecting that said first and second control signals are in predetermined states and turning on said address switch circuit, thereby to enable said memory-cell array, said row address buffer, said row decoder, said sense amplifier, said column address buffer, said column decoder, said input/output gate, and said refresh counter, and supplying the output of said refresh counter to said row address buffer and said column address buffer through said address switch circuit, thereby to set said dynamic memory section into a screening-test mode.

14. The dynamic random access memory according to claim 13, wherein said mode-setting circuit generates a detection signal upon detecting that the first control signal comes to have a level within a range different from a range in which the first control signal is used, after said dynamic memory section has been set into a screening-test mode, thereby to set said dynamic memory section into a write mode.

15. The dynamic random access memory according to claim 13, wherein said mode-setting circuit generates a detection signal upon detecting that the first control signal changes in level after said dynamic memory section has been set into a screening-test mode, thereby to set said dynamic memory section into a write mode.

16. The dynamic random access memory according to claim 14, wherein said mode-setting circuit controls said dynamic memory section such that said dynamic memory section receives the most significant bit output from said refresh counter as input data, while being set in the write mode.

17. The dynamic random access memory according to claim 15, wherein said mode-setting circuit controls said dynamic memory section such that said dynamic memory section receives the most significant bit output from said refresh counter as input data, while being set in the write mode.

18. The dynamic random access memory according to claim 14, wherein said mode-setting circuit controls said dynamic memory section such that said dynamic memory section receives, as input data, data obtained by inverting data supplied from said input/output gate, while being set in the write mode.

19. The dynamic random access memory according to claim 15, wherein said mode-setting circuit controls said dynamic memory section such that said dynamic memory section receives, as input data, data obtained by inverting data supplied from said input/output gate, while being set in the write mode.

20. A dynamic random access memory comprising:

a dynamic memory section including a memory-cell array having dynamic-type memory cells (MC) arranged in rows and columns, a row circuit and a column circuit, both connected to said memory-cell array, and a refresh counter for generating a refresh address signal for refreshing said dynamic-type memory cells when said dynamic memory section is set in a CBR (CAS before RAS) refresh mode;

a first screening-test pad for receiving a first external control signal for setting said dynamic memory section in an ordinary mode or a screening-test mode;

a second screening-test pad for receiving a second external control signal for setting said dynamic memory section in the CBR refresh mode;

a mode-setting circuit for detecting whether the first external control signal and the second external control signal are in predetermined states, for setting said dynamic memory section into a screening-test mode upon detecting that the first and second external control signals are in the predetermined states, and for enabling said row circuit and column circuit upon detecting that the first and second external control signals are in the predetermined states, thereby to cause said refresh counter to supply the refresh address signal to said row circuit and said column circuit,

wherein said dynamic memory section further includes;

a power-supply terminal;

a ground terminal;

a plurality of address terminals for receiving an address signal supplied eternally;

a RAS terminal for receiving a RAS (row address strobe) signal supplied eternally;

a CAS terminal for receiving a CAS (column address strobe) signal supplied eternally;

a WE terminal for receiving a write enable signal supplied externally;

a data output terminal for outputting data to an external device;

a data input terminal for giving data to be written externally;

a row address buffer for receiving a new address signal from one of said address terminals and an output from said refresh counter;

a row decoder for decoding the row address signal supplied from said row address buffer, thereby to select at least one of the rows of memory cells (MC);

a sense amplifier for detecting a potential read from said memory-cell array;

a column address buffer for receiving a column address signal input from said address terminals;

a column decoder for decoding a column address signal supplied from said column address buffer, thereby to select at least one of the columns of memory cells (MC);

an input/output gate for supplying data to and receiving data from at least one selected column of memory cells (MC), in accordance with an output from said column decoder;

a data output buffer for amplifying data read from said input/output gate and outputting the data to said data output terminal;

a data input buffer for amplifying data read from said data input terminal and outputting the data to said data input/output gate;

a control circuit for supplying the output of said refresh counter to said row address buffer when said CAS and RAS signals eternally supplied to said CAS terminal and said RAS terminal, respectively, designate a CBR refresh mode, said mode-setting circuit generating a detection signal upon detecting that said first and second control signals are in predetermined states, thereby to enable said memory-cell array, said row address buffer, said row decoder, said sense amplifier, said column address buffer, said column decoder, said input/output gate, and said refresh counter, and supplying the output of said refresh counter to said row address buffer and said column address buffer, thereby to set said dynamic memory section into a screening-test mode; and

a power-supply voltage lowering circuit for lowering a power-supply voltage applied from said power-supply terminal, thereby to generate an internal power-supply voltage, said mode-setting circuit prohibiting said power-supply lowering circuit from lowering the power-supply voltage when said dynamic memory section is set into the screening-test mode.