Fuzzy multiple signature compaction scheme for built-in self-testing of large scale digital integrated circuits

• US 5,475,694 A
• Filed: 01/19/1993
• Issued: 12/12/1995
• Est. Priority Date: 01/19/1993
• Status: Expired due to Fees

• Current Assignee: University of British Columbia
• Original Assignee: University of British Columbia
• Inventors: Wu, Yuejian, Ivanov, Andre
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): Wachsman, Hal D.
• Application Number:
  US08/005,357
• Time in Patent Office: 1,057 Days
• Field of Search: 371/22.4, 371/26, 371/25.1, 371/28, 371/22.6, 371/15.1, 371/22.3, 371/27, 324/73.1, 324/537
• US Class Current: 714/732
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

A method of testing a digital integrated circuit for faults. A plurality of n check points l₁, l₂, . . . , l_n are established to define a test sequence. A set of m references r₁, r₂, . . . , r_m are predefined, corresponding to the signatures which the circuit would produce at the corresponding check points in the absence of any faults. A test sequence is applied to the circuit and an output signature s_i is derived from the circuit at the corresponding check point l_i. The output signature is compared with each member of the set of references. The circuit is declared "good" if the signature matches at least one member of the set of references, or "bad" if a signature matches no members of the set of references. Testing proceeds in similar fashion at the next check point, until the circuit has been tested at all check points.

Claims

1. A method of testing a digital integrated circuit for faults, said digital integrated circuit comprising one or more inputs and one or more outputs, wherein the state of said one or more outputs of said digital integrated circuit is responsive to signals at said one or more inputs, said method comprising the steps of:

(a) providing a means to apply a sequence of test vectors to said one or more inputs of said digital integrated circuit;

(b) providing a means to generate a signature s_i determined by a sequence of states of said one or more outputs of said digital integrated circuit;

(c) selecting a sequence of test vectors;

(d) establishing a plurality of n check points l₁, l₂, . . . , l_n, where n>

1, in said sequence of test vectors;

(e) defining a set of m reference vectors, r₁, r₂, . . . , r_m, where m>

1, said set of m reference vectors corresponding to signatures produced by said digital integrated circuit at said check points l₁, l₂, . . . , l_n in the absence of any faults in said digital integrated circuit,

(f) applying said sequence of test vectors to said one or more inputs of said digital integrated circuit to cause said one or more outputs of said digital integrated circuit to pass through a sequence of states of said one or more outputs;

(g) at each check point l_i, where l≦

i≦

n, of said plurality of n check points;

(i) deriving a signature s_i from a sub-sequence of states of said one or more outputs of said digital integrated circuit said sub-sequence of states ending at said check point l_i ;

(ii) comparing said derived signature s_i with reference vectors from said set of m reference vectors;

(iii) rejecting said digital integrated circuit if said derived signature does not match any of said set of m reference vectors; and

(h) passing said digital integrated circuit if each derived signature s_i matches at least one member of said set of m reference vectors.

2. The method of claim 1 wherein said means to generate a signature s_i representative of a sequence of states of said one or more outputs of said digital integrated circuit comprises a data compactor and said step of deriving a signature s_i from said sub-sequence of states of said outputs of said digital integrated circuit at said check point l_i comprises compacting a vector corresponding to said sub-sequence of states of said one or more outputs of said digital integrated circuit in said data compactor.

3. The method of claim 2 where m=n.

4. The method of claim 2 where m>

n.

5. The method of claim 2 where 1<

m<

n.

6. The method of claim 2 where m=1 and n is greater than 1.

7. A method of testing a digital integrated circuit for faults, comprising the steps of:

(a) establishing a plurality of n check points l₁, l₂, . . . , l_n, where n>

1 in a test sequence;

(b) defining a set of m references, r₁, r₂, . . . , r_m, where m>

1, said set of m references corresponding to signatures produced by said digital integrated circuit at said plurality of n check points l₁, l₂, . . . , l_n in the absence of any faults in said digital integrated circuit;

(c) applying said test sequence to said digital integrated circuit;

(d) for each check point l_i, where 1≦

i≦

n, of said plurality of n check points;

(i) deriving a signature s_i from said digital integrated circuit at said check point l_i ;

(ii) comparing said derived signature s_i with members of said set of m references;

(iii) rejecting said digital integrated circuit if said derived signature does not match any of said members of said set of m references; and

(e) passing said digital integrated circuit if each derived signature s_i matches at least one member of said set of m references.

8. The method of claim 7 where m=n.

9. The method of claim 7 where m>

n.

10. The method of claim 7 where 1<

m<

n.

11. The method of claim 7 where m=1 and n is greater than 1.

12. A method of testing a digital integrated circuit for faults, said method comprising the steps of:

(a) selecting a sequence of test vectors to apply to said digital integrated circuit;

(b) breaking said sequence of test vectors into a plurality of n sub-sequences, each of said plurality of n sub-sequences terminating at one of a plurality of n check points l₁, l₂, . . . , l_n ;

(c) defining a set of m references r₁, r₂, . . . , r_m corresponding to signatures produced by said digital integrated circuit at said plurality of n check points l₁, l₂, . . . , l_n in the absence of any faults in said digital integrated circuit;

(d) applying said sequence of test vectors to said digital integrated circuit and, at each check point l_i, where 1≦

i≦

n, of said plurality of n check points;

(i) deriving a signature s_i from said digital integrated circuit at said check point l_i ;

(ii) comparing said derived signature s_i with said set of m references to determine whether or not said derived signature s_i matches any member of said set of m references;

(iii) passing said digital integrated circuit if, at all of said plurality of n check points, said derived signature s_i matches at least one member of said set of m references; and

,

(iv) rejecting said digital integrated circuit if, at any of said plurality of n check points, said derived signature s_i matches no members of said set of m references.

13. The method of claim 12 where m=n.

14. The method of claim 12 where m>

n.

15. The method of claim 12 where 1<

m<

n.

16. The method of claim 12 where m=1 and n is greater than 1.

17. The method of claim 12 wherein said sub-sequences are not all identical.

18. The method of claim 12 wherein said sub-sequences are not all equal in length.