Packet video signal inverse transport processor memory address circuitry
First Claim
1. Apparatus in an audio/video signal transport processor for processing signal including time division multiplexed packets of program components, wherein respective packets include a payload of component data and a header including a component identifier, SCID, and wherein respective payloads are extracted from respective packets and stored in buffer memory, circuitry for addressing said buffer memory comprising;
- a source (12) of time division multiplexed packets;
a detector (15), responsive to respective headers for detecting packets having predetermined identifiers;
a control apparatus (19) programmed to generate a plurality of N-bit start and end pointers to allocate a plurality of blocks of said buffer memory for storage of packets of a plurality of program components (N an integer);
first and second like pluralities of registers (87,
88) for storing said plurality of N-bit start pointers and N-bit end pointers respectively;
third and fourth like pluralities of registers (83,
92) for storing N-bit head (write) pointers and N-bit tail (read) pointers respectively, wherein a set of registers, one from each of said first, second, third and fourth pluralities are assigned to each respective program component;
wherein for respective sets of registers;
circuitry (93,
96) for concatenating M bits of said start pointer with said N-bit head pointer to form an N+M-bit write address (M an integer less than N);
circuitry (93,
94) for concatenating M bits of said tart pointer with said N-bit tail pointer to form an N+M-bit read address;
multiplexing (82, 86, 89,
90) means for multiplexing one of said read or write addresses to an address input port of said buffer memory.
1 Assignment
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Accused Products
Abstract
In an inverse transport processor, program component packet payloads of respective program components are directed to select areas of random access memory (RAM) (18) in accordance with a plurality of start and end pointers which are stored in a first plurality (86, 89) of registers, one for each program component. Addresses are generated, in part, by a plurality of read pointer registers (82) multiplexed with an adder (80) to successively increment the pointers for respective program components. The start pointers are associated with read pointers to from memory addresses that scroll through designated memory blocks selectively assigned to respective program components. Memory access for read and write functions are arbitrated (98) so that no incoming program data can be lost, and all component processors are serviced.
131 Citations
20 Claims
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1. Apparatus in an audio/video signal transport processor for processing signal including time division multiplexed packets of program components, wherein respective packets include a payload of component data and a header including a component identifier, SCID, and wherein respective payloads are extracted from respective packets and stored in buffer memory, circuitry for addressing said buffer memory comprising;
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a source (12) of time division multiplexed packets; a detector (15), responsive to respective headers for detecting packets having predetermined identifiers; a control apparatus (19) programmed to generate a plurality of N-bit start and end pointers to allocate a plurality of blocks of said buffer memory for storage of packets of a plurality of program components (N an integer); first and second like pluralities of registers (87,
88) for storing said plurality of N-bit start pointers and N-bit end pointers respectively;third and fourth like pluralities of registers (83,
92) for storing N-bit head (write) pointers and N-bit tail (read) pointers respectively, wherein a set of registers, one from each of said first, second, third and fourth pluralities are assigned to each respective program component;wherein for respective sets of registers; circuitry (93,
96) for concatenating M bits of said start pointer with said N-bit head pointer to form an N+M-bit write address (M an integer less than N);circuitry (93,
94) for concatenating M bits of said tart pointer with said N-bit tail pointer to form an N+M-bit read address;multiplexing (82, 86, 89,
90) means for multiplexing one of said read or write addresses to an address input port of said buffer memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. Apparatus in an audio/video signal transport processor for processing signal including time division multiplexed packets of program components, wherein respective packets include a payload of program component data and a header including a program component identifier, SCID, and wherein respective payloads are stored in buffer memory, circuitry for addressing said buffer memory comprising;
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a source of time division multiplexed packets; a detector, responsive to respective headers for detecting packets having predetermined identifiers; a control apparatus programmed to generate a plurality of N-bit start and end pointers to allocate a plurality of blocks of said buffer memory for storage of packet payloads of a plurality of program components (N an integer); first and second like pluralities of registers for storing said plurality of N-bit start pointers and N-bit end pointers respectively; a third plurality of registers for storing N-bit head (write) pointers, wherein a set of registers, one from each of said first, second and third pluralities are assigned to each respective program component; wherein for respective sets of registers; circuitry for concatenating M bits of said start pointer with said N-bit head pointer to form an N+M-bit write address (M an integer less than N); and means for applying respective said write addresses to an address input port of said buffer memory. - View Dependent Claims (15, 16, 17, 18, 19)
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20. In a packet signal transport processor for processing signal packets of first and second types, basic and auxiliary, and respective packets having identifiers for denoting a program component contained in the corresponding packet payload, apparatus comprising:
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a memory for storing packet payloads; first direct memory access means for generating memory addresses for storing payloads of basic packets in said memory; second direct memory access means for generating addresses for storing payloads of auxiliary packets in said memory, wherein said second direct memory access means generates addresses at least in part, as a function of an identifier associated with the current auxiliary packet.
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Specification