Dynamic look-aside table for multiple size pages

• US 5,475,827 A
• Filed: 04/01/1994
• Issued: 12/12/1995
• Est. Priority Date: 03/13/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Stanton, Robert J. Jr., Lee, Jeffery Y., Mirza, Jamshed H.
• Primary Examiner(s): Lane, Jack A.
• Application Number:
  US08/223,366
• Time in Patent Office: 620 Days
• Field of Search: 395/400, 395/425, 365/49
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2212/652 Page size control
• CPC Class Codes: G06F 2212/681 Multi-level TLB, e.g. microTLB and main TLB

Abstract

A dynamic address translation (DAT) mechanism which supports virtual memory pages of different sizes with minimal hardware and design impact. The dynamic look-aside table (DLAT) is modified to allow the addition of a second page size to system architecture. In one approach, the DLAT is divided into two sections, one for small (4KB) pages and one for large (1MB) pages. A steering table indicates whether the segment last contained 4KB pages or a 1MB page. As each segment is translated by the DAT mechanism, the page size (1MB or 4KB) contained in the segment is known, and this information is used to select the address bus used for indexing the DLAT. In an alternative approach, the DLAT is not divided into sections; rather, it can interchangeably hold/test/select either of the two different formats in any entry. The steering table dynamically changes the way in which the DLAT is addressed and selects the bits of the entry to be used in the translation.

Claims

1. An address translation mechanism for a virtual storage system in a data processing system which supports a plurality of page sizes, comprising:

means for storing virtual addresses to be translated to real addresses, each of said virtual addresses being composed of segment index bits, page index bits and displacement index bits, each of said virtual addresses having a plurality of subsets of bits;

a single dynamic look-aside table for simultaneously storing, for all said plurality of page sizes, translations of said virtual addresses to real addresses, said plurality of page sizes having indices associated therewith;

steering table means for storing said indices of said plurality of page sizes of translations and selecting a correct index for a virtual address to be translated when said steering table means is addressed by segment index bits of said virtual address to be translated; and

means responsive to the correct index selected for selecting out of said plurality of subsets of bits of said virtual address to be translated one subset which corresponds to a page size of said virtual address to be translated for addressing said dynamic look-aside table.

2. The address translation mechanism recited in claim 1 wherein said dynamic look-aside table is divided into at least two sections corresponding to said at least two sizes of pages, and said means for selecting comprises a selector controlled by said steering table means to pass at least a selected group of virtual address bits for addressing said dynamic look-aside table depending on whether the history stored in said steering table means for the segment index bits of said virtual address to be translated indicates that the segment contained a first or a second page size respectively.

3. The address translation mechanism set forth in claim 2 wherein said virtual address to be translated includes address bits, said address translation mechanism further including:

comparison means for comparing said address bits of said virtual address to be translated with virtual bits read out of said single dynamic look-aside table in response to said one subset;

multiple register means coupled to said means for storing virtual addresses to be translated and said single dynamic look-aside table for storing different possible real addresses made up of combinations of real and virtual address bits read from the means for storing virtual addresses to be translated and said single dynamic look-aside table; and

means responsive to said comparison means to select one of said possible real addresses as a real address translation for said virtual address to be translated.

4. The address translation mechanism as recited in claim 1, wherein said single dynamic look-aside table includes a plurality of addresses,

wherein translations, for a plurality of different page sizes for said virtual addresses to real addresses are interspersed within said plurality of addresses in said dynamic look-aside table such that a translation for a first page size of said plurality of different page sizes and a translation for a second page size if said plurality of different page sizes are located at adjacent addresses of said plurality of addresses of said single dynamic look-aside table.

5. The address translation mechanism set forth in claim 4, wherein said virtual address to be translated includes bit positions having page address bits therein and said dynamic look-aside table includes virtual bits, said virtual bits being located in bit positions of said dynamic look-aside table which correspond to those of said virtual address to be translated, said address translation mechanism further including:

comparison means for comparing page address bits from said bit positions of said virtual address to be translated with said virtual bits, in said bit positions which correspond to those of said virtual address to be translated read out of said dynamic look-aside table in response to said one subset; and

means responsive to said comparison means for generating a real address translation of said virtual address to be translated said means for generating including means for selecting one of different possible combinations of virtual and real address bits stored in the means for storing virtual addresses to be translated and said single dynamic look-aside table.