Structure and method for providing a reconfigurable emulation circuit without hold time violations

• US 5,475,830 A
• Filed: 01/31/1992
• Issued: 12/12/1995
• Est. Priority Date: 01/31/1992
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Li, Jeong-Tyng, Huang, Thomas B., Wang, Ming-Yang, Chen, Nang-Ping, Ko, Robert J.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Fiul, Dan
• Application Number:
  US07/829,181
• Time in Patent Office: 1,411 Days
• Field of Search: 364/489, 364/578, 364/488, 375/107, 307/272.2, 395/500
• US Class Current: 716/108
• CPC Class Codes: A21B 1/245 with a plurality of air nozzles to obtain an impingement effect on the food
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partition the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.

Claims

1. In implementing an emulation circuit from a netlist description of a design, said design receiving a plurality of clock sources, a method comprising the steps of:

analyzing said netlist description to identify, for each storage instance receiving a clock signal in said design, a clock path connecting said clock signal to one of said clock sources from which said clock signal is derived; and

implementing a predetermined clock path portion in a programmable logic device circuit dedicated for clock generation, said predetermined clock path portion creating global clock signals.

2. A method as set forth in claim 1, further comprising the steps of:

identifying, for each of said storage instances, data paths starting from either (i) an output data terminal of another storage instance, or (ii) a input terminal of said design, and leading to an input terminal of said storage instance, said data paths including combinatorial circuits;

clustering, for each of said storage instance, said storage instance and said data paths in a cluster; and

implementing the netlist description in a plurality of programmable devices, said implementing step including the step of attempting to implement said data paths and said storage instance of said cluster in the same programmable logic device.

3. A method as set forth in claim 2, said method further comprising the step of constructing a connectivity graph for identifying common signals between a pair of clusters, and wherein said step of implementing the netlist description includes the step of attempting to implement a pair of clusters having common signals in the same programmable logic device.

4. A method as set forth in claim 2, further comprising the step of identifying common components between each pair of clusters, and wherein said step of implementing said emulation circuit duplicates, when said clusters are implemented in different programmable logic devices, said common components in each of said different programmable logic devices.

5. A method for implementing a netlist description of an integrated circuit in a plurality of reprogrammable logic circuits, the integrated circuit characterized by a clock path structure and a data path structure, the clock path structure and the data path structure in turn containing a plurality of storage instances with associated clock paths and data paths, said method comprising the steps of:

analyzing the netlist description to extract from the plurality of storage instances the identity of predetermined storage instances in the clock path structure of the integrated circuit being implemented;

forming at least one cluster for each of the plurality of storage instances, each of said clusters containing one of the plurality of storage instances and its associated clock paths and data paths; and

partitioning the netlist description into a plurality of partitions suitable for respective implementation into said plurality of reprogrammable logic circuits, said partitioning including the step of assigning each of said clusters to at least one of said plurality of partitions such that a predetermined number of said clusters containing said predetermined storage instances are assigned to a predetermined one of said plurality of partitions.

6. The method of claim 5 further comprising the following steps:

identifying all of the clock paths and data paths which are common to more than one of said clusters;

determining when said clusters with said common clock paths and data paths are assigned to separate partitions; and

duplicating said common clock paths and data paths in each partition where said clusters with said common clock paths and data paths appear.

7. A method for implementing a netlist description of an integrated circuit in a plurality of reprogrammable logic circuits, the integrated circuit characterized by a clock path structure and a data path structure, said clock path structure in turn containing clock components, said method comprising the steps of:

analyzing the netlist description to extract the identity of predetermined clock components from the clock path structure of the integrated circuit being implemented; and

partitioning the netlist description into a plurality of partitions suitable for respective implementation into said plurality of reprogrammable logic circuits, said partitioning including the step of assigning each of said predetermined clock components to at least one of said plurality of partitions such that a predetermined number of said predetermined clock components are assigned to a predetermined one of said plurality of partitions.

8. The method of claim 7 wherein the data path structure contains data path components and the clock components include storage instances, said method further comprising the step of forming clusters of clock components and predetermined clock components from the clock path structure and data path components from the data path structure, each cluster comprising a storage instance and its associated clock path structure and data path structure.

9. A method for processing a netlist description of an integrated circuit for implementation in a plurality of reprogrammable logic circuits, the integrated circuit characterized by a clock path structure and a data path structure, the clock path structure and the data path structure including respective clock path components and data path components associated with a plurality of storage instances, said method comprising the steps of:

identifying as common components the associated clock path components and data path components which are input to more than one of the plurality of storage instances;

determining when the storage instances with said common components will be implemented in separate ones of the plurality of reprogrammable logic circuits; and

duplicating said common components in each of said separate ones of the plurality of reprogrammable logic circuits where the storage instances with said common components appear.

10. A method for processing a netlist description of an integrated circuit for implementation in a plurality of reprogrammable logic circuits, the integrated circuit characterized by a clock path structure and a data path structure which collectively include a plurality of storage instances, said method comprising the steps of:

identifying as common structure the associated clock path structure and data path structure which are input to more than one of the plurality of storage instances;

determining when any said common structure will be implemented in separate ones of the plurality of reprogrammable logic circuits; and

duplicating said common structure in each of said separate ones of the plurality of reprogrammable logic circuits.

11. A method for processing a netlist description of an integrated circuit for implementation in a plurality of reprogrammable logic circuits, the integrated circuit characterized by a clock path structure and a data path structure, the clock path structure and the data path structure in turn containing respective clock paths and data paths associated with a plurality of storage instances, said method comprising the steps of:

forming a cluster for each of the plurality of storage instances, each of said clusters containing one of the plurality of storage instances and its associated clock paths and data paths;

identifying all of the associated clock paths and data paths which are common to more than one of said clusters;

determining when said clusters with said common clock paths and data paths are assigned to separate ones of the plurality of reprogrammable logic circuits; and

duplicating all of said common clock paths and data paths in each of said separate ones of the plurality of reprogrammable logic circuits where said clusters with said common clock paths and data paths appear.

12. A method for implementing a netlist description of an integrated circuit in a plurality of reprogrammable logic circuits, the netlist including a plurality of storage instances, said method comprising the steps of:

tracing from a clock input on each of the plurality of storage instances, through a clock path, to a clock source until all of said clock sources are found; and

implementing portions of said clock path starting from said clock source that are foundational to more than one clock signal into a first of said reprogrammable logic circuits.

13. A method for handling a clock path structure of a netlist description of an integrated circuit when implementing the netlist in a plurality of reprogrammable logic circuits comprising the steps of:

analyzing the netlist to identify at least one global clock signal within the netlist, each said global clock signal so identified forming the basis for other clock signals; and

implementing each said global clock signal into a first of the plurality of reprogrammable logic circuits, said first of the plurality of reprogrammable logic circuits dedicated to said global clock signal generation.

14. A method for implementing a netlist description of an integrated circuit design into a plurality of programmable logic circuits, the netlist description having clock structures and data structures and plurality of storage instances, each of the plurality of storage instances having a clock input and data input, the method comprising:

(a) analyzing the clock structures of the netlist description to find any clock sources, clock paths and global clock paths present in the netlist description;

(b) forming clusters, each of said clusters comprising one of the plurality of storage instances and the data structure connected to the data input and the clock structure connected to the clock input of said one of the plurality of storage instances, at least one of said clusters serving as a clock generation storage instance with an associated global clock structure;

(c) identifying the data structures common to more than one of said clusters;

(d) partitioning the netlist into a plurality of partitions, each of which is smaller in size than the total capacity of one of said plurality of reprogrammable logic circuits, each of said plurality of partitions containing at least one of said clusters, a predetermined one of said plurality of partitions comprising a clock generation partition which contains each of said clusters serving as a clock generation storage instance with said associated global clock structure;

(e) duplicating said data structures common to more than one of said clusters in each partition containing a cluster in which the data structures are common to more than one of said clusters; and

(f) placing one of each of said plurality of partitions in one of the plurality of reprogrammable logic circuits such that the reprogrammable logic circuit which receives said clock generation partition serves as a clock generation reprogrammable logic circuit.

15. The method of claim 14 wherein the analyzing step further comprises the steps of:

(a) identifying all clock signals and global clock signals within the netlist description;

(b) marking all user specified clock sources, all clock strobes and all clock qualifiers;

(c) identifying said clock paths by tracing from a clock input terminal or terminals on each of the plurality of storage instances to one of said clock sources;

(d) classifying each of the plurality of storage instances as "clock generation", "external", "same clock", or "different clock";

(e) building clock trees for each of said clock sources; and

(f) analyzing said clock trees in order to select a predetermined number of said global clock signals for implementing in said clock generation reprogrammable logic circuit, said global clock signals being used to derive said clock signals.

16. The method of claim 15 wherein in said marking step, said clock qualifiers are marked by the steps comprising:

(a) marking every user specified clock qualifier as one of said clock qualifiers;

(b) tracing through the clock structure to derive signal nets from each of said clock strobes;

(c) marking output signals of each of the plurality of storage instances that receive a clock input signal from said signal nets as one of said clock qualifiers;

(d) tracing forward from each of said user specified clock sources to the clock input on each of the plurality of storage instances;

(e) backtracking from the clock input through each signal path entering the clock input;

(f) marking all input signals on combinatorial logic of the clock structure encountered in said backtracking step, except for signals previously marked, as one of said clock qualifiers;

(g) marking all data input signals of each of the plurality of storage instances encountered in said backtracking step, except for signals previously marked, as one of said clock qualifiers;

(h) marking outputs of each logic gate of said combinatorial logic as one of said clock qualifiers if every input signal received by said logic gate is either one of said clock qualifiers previously marked or a power signal;

(i) examining said combinatorial logic that receives one of said clock qualifiers to determine whether outputs of said clock qualifiers can be marked as one of said clock qualifiers; and

(j) repeating steps (h)-(i) until all of said clock qualifiers have been marked.

17. The method of claim 15 wherein said classifying step further comprises:

classifying a first storage instance as "clock generation" if a data path leading to the data input on said first storage instance is one of said clock qualifiers;

classifying a second storage instance as "external" if all data paths leading to the data input on said second storage instance are external data paths;

classifying a third storage instance as "same clock" if at least one data path leading to the data input on said third storage instance is at one of a plurality of internal data paths, said one of said plurality of internal data path originating from other storage instances, said other storage instances and said third storage instance being clocked by an identical clock signal; and

classifying a fourth storage instance as "different clock" if at least one data path leading to the data input on said fourth storage instance is one of said plurality of internal data paths, said one of said plurality of internal data paths originating from said other storage instances, said other storage instances and said fourth storage instance being clocked by a different clock signal.

18. A emulation system having a netlist description of an integrated circuit implemented therein, the emulation system comprising:

a plurality of first reprogrammable logic circuits, each of said plurality of first reprogrammable logic circuits having internal circuitry which is configured to provide functional elements selected from the group of at least combinatorial logic elements and storage elements, each of said plurality of first reprogrammable logic circuits also having reprogrammable I/O terminals connected to selected ones of said functional elements configured into said plurality of first reprogrammable logic circuits, said plurality of first reprogrammable logic circuits receiving at least one clock signal;

a selected one of said plurality of first reprogrammable logic circuits having only clock generation structures configured therein;

a plurality of second reprogrammable logic circuits, each of said plurality of second reprogrammable logic circuits having interconnections and data paths implemented therein, each of said plurality of second reprogrammable logic circuits further having reprogrammable I/O terminals and internal circuitry configured to provide interconnections between selected ones of said reprogrammable I/O terminals; and

a set of fixed electrical conductors connecting said reprogrammable I/O terminals on said plurality of first reprogrammable logic circuits to said reprogrammable I/O terminals on said plurality of second reprogrammable logic circuits.

19. The emulation system of claim 18 wherein each of said second reprogrammable logic circuits is connected to at least one but not all of said reprogrammable I/O terminals on each of said plurality of first reprogrammable logic circuits.

20. The emulation system of claim 18 wherein metal conductive traces connect said selected reprogrammable logic circuit to each of said first reprogrammable logic circuits.

21. An apparatus for implementing a netlist into a plurality of reprogrammable logic circuits and a plurality of programmable interconnect integrated circuits, the netlist providing a description of an integrated circuit design having a plurality of storage instances that receive clock signals, combinatorial logic and a plurality of clock sources, the apparatus comprising:

a clock analyzer capable of analyzing the netlist in order to identify a clock path which connects a clock signal generated by a clock source to one of the plurality of storage instances;

a clusterer capable of forming a plurality of clusters, each of said plurality of clusters comprising one of said plurality of storage instances and portions of the combinatorial logic and said clock paths connected to said one of said plurality of storage instances;

a duplicator capable of finding the combinatorial logic common to more than one of said plurality of clusters; and

a partitioner capable of partitioning the netlist into a plurality of partitions, each of said plurality of partitions selected to comprise at least one of said plurality of clusters, said partitioner further placing the combinatorial logic common to more than one of said plurality of clusters into every one of said plurality of partitions containing said plurality of clusters having the combinatorial logic common to more than one of said plurality of clusters.