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Dynamic multi-mode parallel processing array

  • US 5,475,856 A
  • Filed: 10/17/1994
  • Issued: 12/12/1995
  • Est. Priority Date: 11/27/1991
  • Status: Expired due to Term
First Claim
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1. A dynamic multi-mode parallel processing array, comprising:

  • a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory;

    an interconnection path between the instruction registers of the processors;

    the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction;

    the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and

    when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction;

    wherein a controlling processor of a group of processors fetches instructions, and wherein other processors in the group latch into their instruction registers each instruction as the controlling processor fetches it, such that at the end of the instruction fetch all other processors have in their instruction register the fetched instruction; and

    wherein the instruction set includes instructions which modify a processor'"'"'s program counter to function as a base register, including one or more of the following instructions;

    a "Jump" instruction which when executed in a processor operating in SIMD mode sets the processor'"'"'s program counter to a value provide with the jump instruction; and

    a "Load Immediate" instruction which when executed in a processor operating in SIMD mode loads a register with the contents of the processors'"'"' local memory, at the address specified by the processor'"'"'s program counter and then increments the program counter.

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