Input/output control system and method for direct memory transfer according to location addresses provided by the source unit and destination addresses provided by the destination unit
First Claim
1. In a digital data processing apparatus of the type having at least first and second functional units,each of which includes associated memory means for storing data at addressable locations therein,each said memory means being responsive in a read mode to an applied address signal for generating a data signal representative of data stored at a location specified by such address signal, and being responsive in a write mode to applied address and data signals for storing at locations specified by such address signals data specified by such data signal,said data processing apparatus further includingcontroller means coupled to said first and second functional units for transferring data therebetween,the improvement whereinA. said first functional unit includes sender means for generating and transferring to said controller a send MDB signal specifying one or more addresses from which data is to be transferred from the memory means associated with said first functional unit, said second functional unit includes receiver means for generating and transferring to said controller a receive MDB signal specifying one or more addresses to which data is to be transferred in the memory means associated with said second functional unit,B. said controller means includes MDB matching means, coupled to said sender and receiver means, for matching at least a selected one of said send MDB signals to a selected one of said receive MDB signals to generate a signal for effecting the transfer of data between respective locations of the memory means associated with said first and second functional units specified by the matching MDB signals, andC. said controller means further including data transfer means, coupled to said MDB matching means and to the memory means associated with said first and second functional units, for responding to said transfer-effecting signal fori) applying to the memory means associated with the first functional unit an address signal representative of addresses specified in the send MDB signal, and receiving therefrom data signals generated thereby in response to application of that address signal,ii) applying those data signals to the memory means associated with said second functional unit, along with an address signal representative of addresses specified in said receive MDB signal.
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Abstract
A digital data processing apparatus has two functional units (e.g., a host processing section and a peripheral device) and a controller for transferring information therebetween. The first functional unit generates a send message descriptor block ("MDB") signal specifying one or more addresses in an associated local memory from which data is to be transferred. The second functional unit generates a receive MDB signal specifying one or more locations in its associated local memory to which data is to be transferred. The controller matches send and receive MDB signals, particularly, those specifying the same logical or virtual channel. Once a match is found, the controller transfers data between the respective memory locations of the first and second functional units. A controller as described above transfers data between the host and peripheral processors by directly accessing data in their respective "memory spaces."
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Citations
24 Claims
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1. In a digital data processing apparatus of the type having at least first and second functional units,
each of which includes associated memory means for storing data at addressable locations therein, each said memory means being responsive in a read mode to an applied address signal for generating a data signal representative of data stored at a location specified by such address signal, and being responsive in a write mode to applied address and data signals for storing at locations specified by such address signals data specified by such data signal, said data processing apparatus further including controller means coupled to said first and second functional units for transferring data therebetween, the improvement wherein A. said first functional unit includes sender means for generating and transferring to said controller a send MDB signal specifying one or more addresses from which data is to be transferred from the memory means associated with said first functional unit, said second functional unit includes receiver means for generating and transferring to said controller a receive MDB signal specifying one or more addresses to which data is to be transferred in the memory means associated with said second functional unit, B. said controller means includes MDB matching means, coupled to said sender and receiver means, for matching at least a selected one of said send MDB signals to a selected one of said receive MDB signals to generate a signal for effecting the transfer of data between respective locations of the memory means associated with said first and second functional units specified by the matching MDB signals, and C. said controller means further including data transfer means, coupled to said MDB matching means and to the memory means associated with said first and second functional units, for responding to said transfer-effecting signal for i) applying to the memory means associated with the first functional unit an address signal representative of addresses specified in the send MDB signal, and receiving therefrom data signals generated thereby in response to application of that address signal, ii) applying those data signals to the memory means associated with said second functional unit, along with an address signal representative of addresses specified in said receive MDB signal.
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21. An improved method of operating a digital data processing apparatus of the type having
at least first and second functional units, each of which includes associated memory means for storing data at addressable locations therein, each said memory means being responsive in a read mode to an applied address signal for generating a data signal representative of data stored at a location specified by such address signal, and being responsive in a write mode to applied address and data signals for storing at locations specified by such address signals data specified by such data signal, said data processing apparatus further including controller means coupled to said first and second functional units for transferring data there between, the improvement comprising the steps of A. generating within said first functional unit a send MDB signal specifying one or more addresses in the associated memory means from which data is to be transferred, and transferring that send MDB signal to said controller, generating within said second functional unit a receive MDB signal specifying one or more addresses in associated memory means to which data is to be transferred, and transferring that receive MDB signal to said controller, B. matching within said controller at least a selected send MDB signal to a selected receive MDB signal to generate a signal for effecting the transfer of data between respective locations of the memory means of said first and second functional units specified by the matching MDB signals, and C. responding within said controller to said transfer-effecting signal for i) applying to the memory means of the first functional unit an address signal representative of addresses specified in the send MDB signal, and receiving therefrom data signals generated thereby in response to application of that address signal, ii) applying those data signals to the memory means of said second functional unit, along with an address signal representative of addresses specified in said receive MDB signal.
Specification