Input/output control system and method for direct memory transfer according to location addresses provided by the source unit and destination addresses provided by the destination unit

• US 5,475,860 A
• Filed: 06/15/1992
• Issued: 12/12/1995
• Est. Priority Date: 06/15/1992
• Status: Expired due to Term

• Current Assignee: Stratus Computer, Inc. (Stratus Technologies Bermuda Holdings Ltd.)
• Original Assignee: Stratus Computer, Inc. (Stratus Technologies Bermuda Holdings Ltd.)
• Inventors: West, Jonathan, Snapper, William D., Ellison, Carl, Sybel, Randy
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): DINH, DUNG C
• Application Number:
  US07/898,157
• Time in Patent Office: 1,275 Days
• Field of Search: 395/275, 395/200, 395/325, 395/425
• US Class Current: 710/26
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A digital data processing apparatus has two functional units (e.g., a host processing section and a peripheral device) and a controller for transferring information therebetween. The first functional unit generates a send message descriptor block ("MDB") signal specifying one or more addresses in an associated local memory from which data is to be transferred. The second functional unit generates a receive MDB signal specifying one or more locations in its associated local memory to which data is to be transferred. The controller matches send and receive MDB signals, particularly, those specifying the same logical or virtual channel. Once a match is found, the controller transfers data between the respective memory locations of the first and second functional units. A controller as described above transfers data between the host and peripheral processors by directly accessing data in their respective "memory spaces."

Claims

1. In a digital data processing apparatus of the type having at least first and second functional units,

each of which includes associated memory means for storing data at addressable locations therein,

each said memory means being responsive in a read mode to an applied address signal for generating a data signal representative of data stored at a location specified by such address signal, and being responsive in a write mode to applied address and data signals for storing at locations specified by such address signals data specified by such data signal,

said data processing apparatus further including

controller means coupled to said first and second functional units for transferring data therebetween,

the improvement wherein

A. said first functional unit includes sender means for generating and transferring to said controller a send MDB signal specifying one or more addresses from which data is to be transferred from the memory means associated with said first functional unit,

said second functional unit includes receiver means for generating and transferring to said controller a receive MDB signal specifying one or more addresses to which data is to be transferred in the memory means associated with said second functional unit,

B. said controller means includes MDB matching means, coupled to said sender and receiver means, for matching at least a selected one of said send MDB signals to a selected one of said receive MDB signals to generate a signal for effecting the transfer of data between respective locations of the memory means associated with said first and second functional units specified by the matching MDB signals, and

C. said controller means further including data transfer means, coupled to said MDB matching means and to the memory means associated with said first and second functional units, for responding to said transfer-effecting signal for

i) applying to the memory means associated with the first functional unit an address signal representative of addresses specified in the send MDB signal, and receiving therefrom data signals generated thereby in response to application of that address signal,

ii) applying those data signals to the memory means associated with said second functional unit, along with an address signal representative of addresses specified in said receive MDB signal.

2. In a digital data processing apparatus according to claim 1, the further improvement wherein at least one of said first and second functional units comprises command FIFO means for storing one or more MDB signals pending receipt of a match.

3. In a digital data processing apparatus according to claim 2, the further improvement wherein each said command FIFO means comprises means for storing said respective MDB signals in such a way that they can be accessed in an order in which they were received by that command FIFO means.

4. In a digital data processing apparatus according to claim 1, the improvement wherein said MDB matching means comprises virtual channel means for matching MDB signals generated by said first and second functional units along a plurality of virtual channels.

5. In a digital data processing apparatus according to claim 4, the improvement wherein

A. each of said sender means and receiver means includes means for generating said respective send MDB signal and receive MDB signal to include a virtual channel number specifying a virtual channel upon which said matching is to occur,

B. said virtual channel means includes means for responding to send and receive MDB signals having like virtual channel numbers for effecting the transfer of the corresponding data.

6. In a digital data processing apparatus according to claim 5, the improvement wherein said virtual channel means comprises virtual channel memory means for storing at least one of

A. At least a pointer to a send MDB signal pending receipt of a receive MDB signal having a like virtual channel number, and

B. At least a pointer to a receive MDB signal pending receipt of a send MDB signal having a like virtual channel number.

7. In a digital data processing apparatus according to claim 4, the improvement wherein

A. at least one of said first and second functional units comprise means for generating and transmitting to said controller a signal for requesting at least one of creation, flushing, closing, disconnecting and resuming a virtual channel,

B. said virtual channel means comprises connection manager means responsive to such signal for selectively creating, flushing, closing, resuming and disconnecting a selected virtual channel.

8. In a digital data processing apparatus according to claim 7, the improvement wherein

A. each of said sender and receiver means to include means for generating at least one of a channel flushing or channel closing signal, and

B. said connection manager includes channel flushing means responsive to said channel flushing signal for performing at least one of the following operations

(i) clearing a specified virtual channel of any pending MDB signals, and

(ii) returning any pending or en-route MDB signals to the originating one of said respective first and second functional units,

C. said connection manager further includes channel closing means responsive to said channel closing signal for isolating a specified virtual channel from further delivery of any of said send and receive MDB signals.

9. In a digital data processing apparatus according to claim 4, the improvement wherein said MDB matching means comprises a predefined virtual channel for transferring at least signals between said controller and at least one of said first and second functional units.

10. In a digital data processing apparatus according to claim 9, the further improvement wherein said MDB matching means comprises a predefined CONNECTION MANAGER VIRTUAL CHANNEL pair for transferring in two directions between said connection manager means and at least one of said first and second functional units signals representative of requests for connection manager operation and replies thereto.

11. In a digital data processing apparatus according to any of claim 9, the further improvement wherein said MDB matching means comprises a predefined DRIVER CONTROL virtual channel for transferring between any two of said controller, said first functional unit and said second functional unit, at least one of the following

(i) a signal designating a virtual channel upon which a communication transaction is to be effected, and

(ii) control and communication data.

12. In a digital data processing apparatus according to claim 9, the improvement wherein said MDB matching means further comprises at least one of

A. a MAINTENANCE &

DIAGNOSTIC predefined virtual channel for transferring at least one of diagnostic and error signals between at least two of said controller, said first functional unit, and said second functional unit,

B. a DEBUGGER predefined virtual channel for transferring debugging signals between at least two of said controller, said first functional unit, and said second functional unit.

13. In a digital data processing apparatus according to claim 1, the improvement wherein the controller comprises return means responsive to completion of a data transfer for returning control of the corresponding send and receive MDB signals to respective ones of said first and second functional units.

14. In a digital data processing apparatus according to claim 13, the improvement wherein at least one of said first and second functional units further comprises at least one return FIFO means for holding a corresponding MDB signal upon completion of said data transfer.

15. In a digital data processing apparatus according to claim 14, the improvement wherein each of said sender means and receiver means includes means for generating said respective send and receive MDB signal to include a return FIFO number specifying which one of said respective return FIFO means the respective MDB signal is to be returned to.

16. In a digital data processing apparatus according to claim 13, the improvement wherein

A. at least one of said sender and receiver means includes means for generating respective ones of said send and receive MDB signals to include a signal specifying a predetermined operation to be executed upon completion of said data transfer, and

B. said corresponding first and second functional units include callback means for executing said predetermined operation upon return of control of a respective specifying one of said MDB signals.

17. In a digital data processing apparatus according to claim 16, the improvement wherein at least one of said sender and receiver means includes means for generating said signal specifying said predetermined operation to be an address indicative of programming instructions for carrying out that predetermined operation.

18. In a digital data processing apparatus according to claim 1, the improvement wherein

A. said sender means includes means for generating a send MDB structure including at least one or more addresses in the associated memory means from which data is to be transferred, and zero, one or more other data,

B. said receiver means includes means for generating a receiver MDB structure including at least one or more addresses in the associated memory means to which data is to be transferred, and zero, one or more other data,

C. each of said sender and receiver means include means for generating an MDB signal to be a pointer to a respective one of said send and receive MDB structures.

19. In a digital data processing apparatus according to claim 13, the improvement wherein said return means includes means for marking said send and receive MDB signal to include a signal indicative of a status of the requested data transfer.

20. In a digital data processing apparatus according to claim 13, the further improvement wherein said return FIFO means further comprises INTERRUPT buffer means for storing signals representing MDB signals and for generating an interrupt upon receipt thereof.

21. An improved method of operating a digital data processing apparatus of the type having

at least first and second functional units,

each of which includes associated memory means for storing data at addressable locations therein,

each said memory means being responsive in a read mode to an applied address signal for generating a data signal representative of data stored at a location specified by such address signal, and being responsive in a write mode to applied address and data signals for storing at locations specified by such address signals data specified by such data signal,

said data processing apparatus further including

controller means coupled to said first and second functional units for transferring data there between,

the improvement comprising the steps of

A. generating within said first functional unit a send MDB signal specifying one or more addresses in the associated memory means from which data is to be transferred, and transferring that send MDB signal to said controller,

generating within said second functional unit a receive MDB signal specifying one or more addresses in associated memory means to which data is to be transferred, and transferring that receive MDB signal to said controller,

B. matching within said controller at least a selected send MDB signal to a selected receive MDB signal to generate a signal for effecting the transfer of data between respective locations of the memory means of said first and second functional units specified by the matching MDB signals, and

C. responding within said controller to said transfer-effecting signal for

i) applying to the memory means of the first functional unit an address signal representative of addresses specified in the send MDB signal, and receiving therefrom data signals generated thereby in response to application of that address signal,

ii) applying those data signals to the memory means of said second functional unit, along with an address signal representative of addresses specified in said receive MDB signal.

22. A method according to claim 21, the improvement comprising matching said MDB signals generated by said first and second functional units along a plurality of virtual channels.

23. A method according to claim 22, the improvement comprising the steps of

A. generating said send MDB signal and said receive MDB signal to include a virtual channel number specifying a virtual channel over which said matching is to occur,

B. responding within said controller to receipt of send and receive MDB signals having like virtual channel numbers for generating said transfer-effecting signal.

24. A method according to claim 21, comprising the steps of

A. generating within any of said functional units a signal requesting at least one of creation, flushing, closing, disconnecting and resuming a virtual channel,

B. responding to such request signal selectively creating, flushing, closing, resuming and disconnecting the selected virtual channel.