Nonvolatile semiconductor memory device

• US 5,477,068 A
• Filed: 03/17/1993
• Issued: 12/19/1995
• Est. Priority Date: 03/18/1992
• Status: Expired due to Term

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Ozawa, Takanori
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/032,119
• Time in Patent Office: 1,007 Days
• Field of Search: 365/185, 365/900, 365/182, 257/314, 257/315, 257/316, 257/319, 257/320, 257/366
• US Class Current: 257/214
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel

Abstract

A pair of impurity regions are formed at a specified interval in a semiconductor substrate. A channel region is defined between the impurity regions. A select gate is provided on the channel region, and a sidewall for holding electric charge is provided along a side of the select gate. A tunnel insulating film is interposed between the sidewall for holding electric charge and the channel region. An insulating film covers the sidewall for holding electric charge. A control gate is provided on the insulating film lying over the sidewall. In such a structure, since the select gate can have a large cross-sectional area, speed-up of the reading can be attained.

Claims

1. A nonvolatile semiconductor memory device, comprising

a pair of impurity regions, including an impurity region for a source and an impurity region for a drain, formed in a semiconductor substrate at a specified interval;

a channel region between said pair of impurity regions, in the semiconductor substrate;

a select gate formed over said channel region, said select gate having a side close to the drain;

a sidewall structure for holding electric charge, provided along the side of said select gate close to the drain;

a sidewall insulating film covering said sidewall structure;

a tunnel insulating film, interposed between said sidewall structure and said channel region; and

a control gate disposed in a vicinity of said sidewall structure, said sidewall insulating film being interposed between said control gate and said sidewall structure.

2. A nonvolatile semiconductor memory device according to claim 1, wherein said sidewall structure is conductive and functions as a floating gate.

3. A nonvolatile semiconductor memory device according to claim 1, wherein said sidewall structure is an insulating film which can trap electric charge.

4. A nonvolatile semiconductor memory device according to claim 1, wherein said select gate and said control gate are connected to each other and form a unity common gate.

5. A nonvolatile semiconductor memory device according to claim 4, wherein said common gate is formed, extending up to a region above said sidewall structure.

6. A nonvolatile semiconductor memory device according to claim 1, further comprising

(A) writing control means including

(a) means for applying a specified writing voltage between said impurity region for a source and said impurity region for a drain;

(b) means for applying voltage to said select gate to form a channel in said channel region just below said select gate;

(c) means for applying to said control gate voltage by which electric charge in said semiconductor substrate can be pulled into said sidewall structure; and

(d) means for generating hot carriers in said semiconductor substrate in the vicinity of said impurity region for a drain, so that said hot carriers can be injected into said sidewall structure, passing through said tunnel insulating film;

(B) erasing control means,including means for applying a specified erasing voltage between said control gate and the impurity region for a drain, so that electric charge in said sidewall Structure can be pulled out into said impurity region for a drain, passing through said tunnel insulating film; and

(C) reading control means including

(e) means for applying specified voltage to said select gate to form a channel in said channel region just below said select gate;

(f) means for applying to said control gate a specified sense voltage according to which a channel is produced or not in the channel region just below the sidewall structure depending upon whether there is electric charge in said sidewall structure or not; and

(g) means for detecting whether a channel from the impurity region for a source to the impurity region for a drain exists or not.

7. A nonvolatile semiconductor memory device according to claim 6, wherein said writing voltage is a voltage by which of the terminates close to the boundary between a region just below said select gate and a region, just below said sidewall structure.

17. A nonvolatile semiconductor memory device according to claim 1, further comprising an insulating layer interposed between said select gate and said control gate.

18. A nonvolatile semiconductor memory device according to claim 1, wherein said sidewall structure is provided only along said side of said select gate close to said drain.

19. A nonvolatile semiconductor memory device according to claim 1, wherein said sidewall structure comprises means for retaining electrical charges without an external application of a voltage thereto.

8. A nonvolatile semiconductor memory device, comprising

(A) a plurality of memory cells arranged in rows and columns in a matrix manner on a semiconductor substrate, each of which memory cells includes

(a) a pair of impurity regions, including an impurity region for a source and an impurity region for a drain, formed in the semiconductor substrate at a specified interval;

(b) a channel region between said pair of impurity regions in said semiconductor substrate;

(c) a select gate formed over said channel region;

(d) a sidewall structure, for holding electric charge, provided along a side of said select gate close to the drain;

(e) an insulating film covering said sidewall structure;

(f) a tunnel insulating film, interposed between said sidewall structure and said channel region; and

(g) a control gate, disposed in a vicinity of said sidewall structure, the insulating film being interposed between said control gate and said sidewall structure;

(B) for each row, a first word line connected to said select gate of every memory cell aligned in the row;

(C) for said each row, a second word line connected to the control gate of said every memory cell aligned in the row;

(D) for each column, a source line connected to the impurity region for a source of every memory cell aligned in the column;

(E) for said each column, a bit line connected to the impurity region for a drain of said every memory cell aligned in the column;

(F) means for selecting any memory cell in the matrix;

(G) means for, in writing information in the selected memory cell, applying to said first word line connected to the selected memory cell voltage by which a channel is formed in the channel region just below said select gate;

(H) means for, in writing information in the selected memory cell, applying to the second word line connected to the selected memory cell voltage by which electric charge appearing in the channel region is pulled from said sidewall;

(I) means for, in writing information in the selected memory cell, applying between the source line and the bit line connected to the selected memory cell a specified writing voltage by which hot carriers are generated in the channel region just below said sidewall structure;

(J) means for, in erasing information from the selected memory cell, applying between said bit line and said second word line connected to the selected memory cell a specified erasing voltage by which electric charge held in the sidewall structure is pulled out into the impurity region for a drain;

(K) means for, in reading information stored in the selected memory cell, applying to said first word line connected to the selected memory cell voltage by which the channel is formed in the channel region just below said select gate;

(L) means for, in reading information stored in the selected memory cell, applying to said second word line connected to the selected memory cell a specified sense voltage according to which a channel is produced or not in the channel region just below said sidewall structure depending upon whether there is electric charge in said sidewall structure or not; and

(M) information detecting means for, in reading information stored in the selected memory call, detecting whether a channel from said impurity region for a source to said impurity region for a drain in the selected memory cell exists or not.

9. A nonvolatile semiconductor memory device according to claim 8, wherein said information detecting means includes

means for, in reading information stored in the selected memory cell, applying a specified first potential to said source line connected to the selected memory cell;

means for, in reading information stored in the selected memory cell, applying a specified second potential different from the first potential, to said bit line connected to the selected memory cell; and

means for, in reading information stored in the selected memory cell, detecting variations in potential of said bit line connected to the selected memory cell.

10. A nonvolatile semiconductor memory device according to claim 8, wherein said sidewall structure is conductive and acts as a floating gate.

11. A nonvolatile semiconductor memory device according to claim 8, wherein said sidewall structure is an insulating film which can trap electric charge.

12. A nonvolatile semiconductor memory device according to claim 8, wherein said writing voltage is a voltage by which the channel terminates close to the boundary between a region just below said select gate and a region just below said sidewall structure.

13. A nonvolatile semiconductor memory device according to claim 8, wherein said select gate and said control gate are connected to each other to form a unitary common gate, and the first and second word lines are composed of a common line.

14. A nonvolatile semiconductor memory device according to claim 13, wherein said common gate is formed, extending up to a region above said sidewall structure.

15. A nonvolatile semiconductor memory device according to claim 8, wherein each memory cell further comprises an insulating layer interposed between said select gate and said control gate.

16. A nonvolatile semiconductor memory device according to claim 8, wherein said sidewall structure is provided only along said side of said select gate close to said drain.

20. A nonvolatile semiconductor memory device, comprising

a semiconductor substrate;

first and second impurity regions, formed in said semiconductor substrate at a specified interval, one of said first and second impurity regions being a source region and the other of said first and second impurity regions being a drain region;

a channel region in said substrate between said first and second impurity regions, said channel region having a first channel portion adjacent to said first impurity region and a second channel portion between said first channel portion and said second impurity region;

a select gate formed over said second channel portion to control the conductivity of said second channel portion;

a sidewall structure means for selectively holding an electric charge, said sidewall structure means being disposed over said first channel portion and adjacent to a side of said select gate;

a tunnel insulating film, interposed between said sidewall structure and said channel region;

a control gate to selectively control the conductivity of said first channel portion though said sidewall structure means in response to a read voltage applied to said control gate, wherein application of the read voltage to said control gate is effective or ineffective to control the conductivity of said first channel region depending on whether or not said sidewall structure means is holding an electric charge; and

a sidewall insulating film interposed between said sidewall structure and both said select gate and said control gate.

22. A nonvolatile semiconductor memory device according to claim 20, wherein said impurity region for a source, said impurity region for a drain, said control gate and said select gate are responsive to first specified voltages applied thereto to generate hot carriers in said semiconductor substrate in said vicinity of said impurity region for a drain, so that the hot carriers are injected into said sidewall structure, passing through said tunnel insulating film.

23. A nonvolatile semiconductor memory device according to claim 22, wherein said impurity region for a source, said impurity region for a drain, said control gate and said select gate are responsive to second specified voltages applied thereto to draw electric charge from said sidewall structure into said impurity region for a drain, passing through said tunnel insulating film.

24. A nonvolatile semiconductor memory device according to claim 23, wherein said the read voltage has a value intermediate of the first and second specified voltages applied to said control gate.

21. A nonvolatile semiconductor memory device, comprising

a semiconductor substrate;

a pair of impurity regions, including an impurity region for a source and an impurity region for a drain, formed in said semiconductor substrate at a specified interval;

a channel region between said pair of impurity regions, in said semiconductor substrate, said channel region having a first channel portion adjacent to said impurity region for a drain and a second channel portion between said first channel portion and said impurity region for a source;

a first controlling means, including a select gate formed over said channel region, for controlling the conductivity of said second channel portion, said select gate having a side close to said impurity region for a drain;

a sidewall structure for holding an electric charge, provided along said side of said select gate;

a tunnel insulating film, interposed between said sidewall structure and said channel region;

a second controlling means, including a control gate disposed in a vicinity of said sidewall structure, said second controlling means being responsive to a read voltage applied to said control gate, for controlling the conductivity of said first channel portion though said sidewall structure, wherein application of the read voltage to said control gate is effective or ineffective to control the conductivity of said first channel region depending on whether or not said sidewall structure is holding an electric charge film; and

a sidewall insulating film interposed between said sidewall structure and both said select gate and said control gate.