MOS random access memory having array of trench type one-capacitor/one-transistor memory cells

• US 5,477,071 A
• Filed: 04/07/1995
• Issued: 12/19/1995
• Est. Priority Date: 03/19/1992
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hamamoto, Takeshi, Horiguchi, Fumio
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/418,877
• Time in Patent Office: 256 Days
• Field of Search: 257/302, 257/305, 257/301
• US Class Current: 257/302
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.

Claims

1. A semiconductor memory device comprising:

a substrate having a surface in which a plurality of trenches are formed;

a plurality of parallel data transfer lines on said substrate; and

an array of memory cells on said substrate, said memory cells being electrically isolated from each other by a plurality of grooves, said memory cells being divided into a plurality of cell units which are coupled at a node to said data transfer lines, and each of said cell units including a preselected number of memory cells each having a capacitive element and a first and a second transistor;

wherein said capacitive element and said transistors of each of said memory cells are stacked in a corresponding one of said trenches in such a manner that said transistors overlie said capacitive element in said corresponding one of said trenches,

said transistors comprise;

an insulated gate electrode commonly used for said transistors and insulatively disposed above said capacitive element in said corresponding one of said trenches;

a first impurity-doped carrier-conveying region arranged around said corresponding one of said trenches in said substrate and coupled to said capacitive element;

a second impurity-doped carrier-conveying region arranged in said substrate to define a first channel region of said first transistor between the first and second regions in said substrate; and

a third impurity-doped carrier-conveying region arranged in said substrate at an opposite side of said second region with said gate electrode interposing therebetween to define a second channel region of said second transistor between the second and the third regions,

each of said memory cells comprises said first transistor and said second transistor, thereby to form a preselected number of first transistors and second transistors, which include the preselected number of said third regions, corresponding to the preselected number of said memory cells, and

said preselected number of said memory cells are series-connected in such a manner that said third region of one of said second transistors is connected to said second region of another of said second transistors adjacent to said one second transistor and that a terminal one of said third regions forms said node at which each of said cell units is coupled to a corresponding one of said data transfer lines.

2. The device according to claim 1, wherein said capacitive element comprises a conductive layer insulatively buried in said corresponding one of said trenches for storing electrical carriers therein.

3. The device according to claim 1, wherein said substrate comprises:

said grooves formed in the substrate surface to define a plurality of rows and columns of island portions in which said trenches for said memory cells are formed; and

insulative layers buried in said grooves for causing adjacent ones of said transistors of said memory cells to be electrically separated from each other.

4. The device according to claim 3, wherein said grooves are less in depth than said trenches.

5. The device according to claim 4, wherein said grooves include:

first parallel grooves extending in a first direction in said substrate; and

second parallel grooves extending in a second direction transverse to said first direction.

6. The device according to claim 5, wherein said substrate comprises:

a heavily-doped semiconductive substrate of a selected type of conductivity; and

a semiconductive region arranged in a surface section of said heavily-doped substrate, said first, second and third carrier-conveying regions being formed in said semiconductive region, said trenches being greater in depth than said semiconductive region for allowing said conductive layer to face said heavily-doped substrate.

7. The device according to claim 6, wherein said first carrier-conveying region is arranged at a limited portion of said semiconductive region which is partially contacted with the corresponding one of said trenches.

13. The device according to claim 1, comprising:

said first transistor having an active region formed on a side wall portion of said trench in contact with said capacitive element; and

said plurality of grooves extending into said substrate to a depth greater than a depth of said active region.

14. The device according to claim 1, comprising:

said plurality of grooves extending into said substrate to a depth greater than a depth of said trench.

15. The device according to claim 1, comprising:

said second transistor of each of said memory cells having an active region formed at a surface of said substrate adjacent to one of said plurality of grooves; and

a number of said second transistors being series-connected to provide a NAND cell arrangement using a conductive layer formed over said plurality of grooves and in contact with active regions of two adjacent island portions.

8. A semiconductor memory device comprising:

a substrate having a surface in which a pattern of grooves is formed to provide a plurality of rows and columns of island portions, and having a plurality of trenches formed in said island portions;

an array of memory cells arranged in rows and columns at said island portions, said memory cells being divided into a plurality of cell units in which a preselected number of said memory cells are series-connected in a column direction, said memory cells each including a capacitor and a first and a second metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of said trenches;

parallel word lines coupled to the rows of memory cells, respectively;

parallel bit lines coupled to said cell units, respectively; and

insulative layers buried in said grooves for causing adjacent ones of said island portions to be electrically isolated from each other,

wherein said capacitor includes a carrier-storage layer which is insulatively disposed in the corresponding one of said trenches;

said MOS transistors include;

an insulated gate electrode commonly used for said transistors and stacked above said carrier-storage layer in the corresponding one of said trenches;

,

a first impurity-doped semiconductor region arranged around said corresponding one of said trenches in said substrate so as to be directly contacted with a carrier-storage layer of said capacitor in a selected sidewall area of said corresponding one of said trenches;

a second impurity-doped semiconductive region arranged in the corresponding one of said island portions on a top surface thereof to define a first channel region of said first transistor between the first and second regions along said gate electrode; and

a third impurity-doped semiconductive region arranged in the corresponding one of said island portions on a top surface thereof at an opposite side of the second region with said gate electrode intervening therebetween to provide a second channel region of said second transistor along said gate electrode,

each of said memory cells comprises said first transistor and said second transistor, thereby to form a preselected number of first transistors and second transistors, which include the preselected number of said third regions, corresponding to the preselected number of said memory cells, and

said preselected number of said memory cells are series-connected in such a manner that said third region of one of said second transistors is connected to said second region of another of said second transistors adjacent to said one second transistor, and that a terminal one of said third regions is coupled to a corresponding one of said bit lines, and

a depth of said grooves is deeper than that of said first impurity-doped semiconductor region arranged around said corresponding one of said trenches.

9. The device according to claim 8, wherein said word lines comprise:

a plurality of elongate conductive layers extending on the row of said island portions.

10. The device according to claim 9 wherein said trenches are greater in depth than said grooves.

11. The device according to claim 8, wherein said bit lines comprise:

conductive wiring means on said island portions, for causing second impurity-doped semiconductive regions of the columns of said island portions to be electrically connected together.

12. The device according to claim 11, wherein said conductive wiring means includes:

a plurality of conductive layers arranged among said elongate conductive layers on said island portions, each of said conductive layers being formed to bridge an insulator-buried groove between adjacent ones of said columns of island portions to cause the second impurity-doped semiconductive regions thereof to be coupled to each other.

16. The device according to claim 8, comprising:

said plurality of grooves extending into said substrate to a depth greater than a depth of said trench.

17. The device according to claim 8, comprising:

said second transistor of each of said memory cells having an active region formed at a surface of said island portion adjacent to one of said plurality of grooves; and

a number of said second transistors being series-connected to provide a NAND cell arrangement using a conductive layer formed over said plurality of grooves and in contact with active regions of two adjacent island portions.