Probeable substrate substitute for a calibration standard and test fixture

• US 5,477,137 A
• Filed: 10/02/1992
• Issued: 12/19/1995
• Est. Priority Date: 10/02/1992
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Staudinger, Joseph, Seely, Warren L., Golio, John M.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/955,967
• Time in Patent Office: 1,173 Days
• Field of Search: 324/158 R, 324/158 F, 324/73.1, 324/158 P, 324/765, 333/246, 333/248, 333/247, 361/778, 361/790, 361/779, 361/792, 174/261, 439/55, 439/60, 439/66, 439/70, 257/691, 257/676
• US Class Current: 324/754.03
• CPC Class Codes: G01R 1/04 Housings; Supporting members; Arrangements of terminals
• CPC Class Codes: G01R 35/02 of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating

Abstract

A method and apparatus for a probeable substrate substitute for a calibration standard and test fixture. The probestrate includes a dielectric substrate having first and second dielectric substrate surfaces and at least one conductive via hole through the dielectric substrate from the first dielectric substrate surface to the second dielectric substrate surface. A first metalized layer is in contact with the first dielectric substrate surface and the at least one conductive via hole. A second metalized layer is in contact with a first portion of the second dielectric substrate surface and with the at least one conductive via hole. The first and second test ports contact a second portion of the second dielectric substrate surface. An electronic device can be connected to the first and second test ports with bond wires for characterization via contact of the first and second test ports with standard test station equipment.

Claims

1. A probeable substrate for receiving an electronic device, the probeable substrate comprising:

a dielectric substrate having first and second dielectric substrate surfaces and at least one conductive via hole through the dielectric substrate from the first dielectric substrate surface to the second dielectric substrate surface;

a first metalized layer in contact with the first dielectric substrate surface and the at least one conductive via hole;

a second metalized layer in contact with a first portion of the second dielectric substrate surface and in contact with the at least one conductive via hole; and

first and second test ports in contact with a second portion of the second dielectric substrate surface;

wherein the electronic device is connected to the first and second test ports for probing via the first and second test ports.

2. A probeable substrate as claimed in claim 1, wherein the first and second dielectric substrate surfaces are substantially parallel.

3. A probeable substrate as claimed in claim 1, wherein the first and second test ports comprise coplanar transmission lines.

4. A probeable substrate as claimed in claim 1, wherein the electronic device is a microwave monolithic integrated circuit (MMIC) device.

5. A probeable substrate as claimed in claim 1, wherein the second metalized layer and the first and second test ports substantially cover the second dielectric substrate surface.

6. A probeable substrate as claimed in claim 5, wherein the second metalized layer and the first and second test ports substantially cover the second dielectric substrate surface except for a first gap between the first test port and the second metalized layer and a second gap between the second test port and the second metalized layer, where dimensions of the first and second gaps are determined by the material and dimensions of the probeable substrate and the electronic device is placed on the second metalized layer between the first and second test ports during probing.

7. A probeable substrate as claimed in claim 1, wherein the second metalized layer does not extend between the first and second test ports and the electronic device is placed on the second dielectric substrate surface during probing.

8. A test fixture for probing an integrated circuit comprising:

a dielectric substrate having first and second dielectric substrate surfaces and at least one conductive via hole through the dielectric substrate from the first dielectric substrate surface to the second dielectric substrate surface;

a first metalized layer in contact with the first dielectric substrate surface and in contact with the at least one conductive via hole;

a second metalized layer in contact with a first portion of the second dielectric substrate surface and in contact with the at least one conductive via hole; and

first and second test ports in contact with a second portion of the second dielectric substrate surface;

wherein the integrated circuit is connected to the first and second test ports for probing via the first and second test ports.

9. A test fixture as claimed in claim 8, wherein the first and second dielectric substrate surfaces are substantially parallel.

10. A test fixture as claimed in claim 8, wherein the first and second test ports comprise coplanar transmission lines.

11. A test fixture as claimed in claim 8, wherein the electronic device is a microwave monolithic integrated circuit (MMIC) device.

12. A test fixture as claimed in claim 8, wherein the second metalized layer and the first and second test ports substantially cover the second dielectric substrate surface except for a first gap between the first test port and the second metalized layer and a second gap between the second test port and the second metalized layer, where dimensions of the first and second gaps are narrower than dimensions of the test fixture;

and

the electronic device is placed on the second metalized layer between the first and second test pods during probing.

13. A test fixture as claimed in claim 8, wherein the second metalized layer does not extend between the first and second test ports and the electronic device is placed on the second dielectric substrate surface during probing.