Method and structure for improving patterning design for processing

• US 5,477,466 A
• Filed: 12/22/1994
• Issued: 12/19/1995
• Est. Priority Date: 07/19/1991
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Wang, Chi-Hung, Whitefield, Bruce, Tripathi, Prabhakar P.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/362,839
• Time in Patent Office: 362 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 430/5, 430/269, 430/296, 430/311, 250/492.2, 250/492.3
• US Class Current: 430/318
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.

Claims

1. A method of fabricating an integrated circuit, comprising the steps of:

(a) generating a circuit layout of said integrated circuit, comprising the substeps of;

(a1) determining a surface area of metallization used in said circuit layout;

(a2) comparing said surface area with a first predetermined value;

(a3) determining a distance between a first working line and a second working line to determine if said first or said second working line is a lonely line;

(a4) comparing said distance to a second predetermined value; and

if said distance is greater than said second predetermined value,

(a5) placing a dummy line at a predetermined distance from said lonely line;

(b) forming active regions on an integrated circuit chip;

(c) forming a metallization layer on the chip;

(d) forming a photoresist layer on the metallization layer;

(e) imaging the photoresist layer in accordance with said circuit layout;

(f) developing the photoresist layer;

(g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and

(h) removing the photoresist layer.

2. A method as in claim 1, in which step (a) further comprises the substep of:

(a6) repeating steps (a1) through (a5) until said area is at least said first predetermined value.

3. A method as in claim 2, in which step (a) further comprises the substep of:

(a7) distinguishing said dummy line from said working line;

wherein step (a7) follows step (a3).

4. A method of fabricating an integrated circuit, comprising the steps of:

(a) generating a circuit layout using a computer, comprising the substeps of;

(a1) determining a surface area of said metallization;

(a2) comparing said area with a first predetermined value;

if said area is less than said first predetermined value, said computer proceeding with the following series of substeps;

(a3) initializing a mesh pattern of local wires with physical wires;

(a4) removing an overlap between said local and said physical wires;

(a5) removing portions of said local wires which are within a first predetermined distance from said physical wires;

(a6) removing segments of said local wires of a length less than a second predetermined value;

(a7) creating a boundary of a second predetermined distance surrounding said physical wires; and

(a8) removing segments of said local wires which are outside said boundary;

(b) forming active regions on an integrated circuit chip;

(c) forming a metallization layer on the chip;

(d) forming a photoresist layer on the metallization layer;

(e) imaging the photoresist layer in accordance with said circuit layout;

(f) developing the photoresist layer;

(g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and

(h) removing the photoresist layer.

5. A method as in claim 4, in which step (a) further comprises the substeps of:

(a9) changing the characterization of said local wires causing said local wires to appear as physical wires; and

(a10) repeating steps (a1) through (a8) until said area is greater than said first predetermined value.

6. A method as in claim 5, in which step (a) further comprises the substep of:

(a11) distinguishing said local wires from said physical wires;

wherein step (a11) follows said step (a8).

7. A method of fabricating an integrated circuit, comprising the steps of:

(a) generating a circuit layout of said integrated circuit, comprising the substeps of;

(a1) determining a surface area of a layer of metallization used in said circuit;

(a2) comparing said surface area with a first predetermined value;

if said area is less than said first predetermined value, proceeding with the following series of steps;

(a3) initializing a mesh pattern of local wires with physical wires;

(a4) removing an overlap between said local and said physical wires;

(a5) removing portions of said local wires which are within a first predetermined distance from said physical wires;

(a6) removing segments of said local wires of a length less than a second predetermined value;

(a7) creating a boundary of a second predetermined distance surrounding said physical wires; and

(a8) removing segments of said local wires which are outside said boundary;

(b) forming active regions on an integrated circuit chip;

(c) forming a metallization layer on the chip;

(d) forming a photoresist layer on the metallization layer;

(e) imaging the photoresist layer in accordance with said circuit layout;

(f) developing the photoresist layer;

(g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and

(h) removing the photoresist layer.

8. A method as in claim 7, in which step (a) further comprises the substeps of:

(a9) changing the characterization of said local wires causing said local wires to appear as physical wires; and

(a10) repeating steps (a1) through (a8) until said area is greater than said first predetermined value.

9. A method as in claim 8, in which step (a) further comprises the substep of:

(a11) distinguishing said local wires from said physical wires;

wherein step (a11) follows said step (a8).

10. A method of forming metallization on an integrated circuit, comprising the steps of:

(a) generating a circuit layout of said integrated circuit, comprising the substeps of;

(a1) determining a surface area of metallization used in said circuit layout;

(a2) comparing said surface area with a first predetermined value;

(a3) determining a distance between a first working line and a second working line to determine if said first or said second working line is a lonely line;

(a4) comparing said distance to a second predetermined value; and

if said distance is greater than said second predetermined value,

(a5) placing a dummy line at a predetermined distance from said lonely line;

(b) forming a metallization layer on an integrated circuit chip;

(c) forming a photoresist layer on the metallization layer;

(d) imaging the photoresist layer in accordance with said circuit layout;

(e) developing the photoresist layer;

(f) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and

(g) removing the photoresist layer.

11. A method as in claim 10, in which step (a) further comprises the substep of:

(a6) repeating steps (a1) through (a5) until said area is at least said first predetermined value.

12. A method as in claim 11, in which step (a) further comprises the substep of:

(a7) distinguishing said dummy line from said working line;

wherein step (a7) follows step (a3).

13. A method of forming metallization on an integrated circuit, comprising the steps of:

(a) generating a circuit layout using a computer, comprising the substeps of;

(a1) determining a surface area of said metallization;

(a2) comparing said area with a first predetermined value;

if said area is less than said first predetermined value, said computer proceeding with the following series of substeps;

(a3) initializing a mesh pattern of local wires with physical wires;

(a4) removing an overlap between said local and said physical wires;

(a5) removing portions of said local wires which are within a first predetermined distance from said physical wires;

(a6) removing segments of said local wires of a length less than a second predetermined value;

(a7) creating a boundary of a second predetermined distance surrounding said physical wires; and

(a8) removing segments of said local wires which are outside said boundary;

(b) forming a metallization layer on an integrated circuit chip;

(d) forming a photoresist layer on the metallization layer;

(e) imaging the photoresist layer in accordance with said circuit layout;

(f) developing the photoresist layer;

(g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and

(h) removing the photoresist layer.

14. A method as in claim 13, in which step (a) further comprises the substeps of:

(a9) changing the characterization of said local wires causing said local wires to appear as physical wires; and

(a10) repeating steps (a1) through (a8) until said area is greater than said first predetermined value.

15. A method as in claim 14, in which step (a) further comprises the substep of:

(a11) distinguishing said local wires from said physical wires;

wherein step (a11) follows said step (a8).

16. A method of forming metallization on an integrated circuit, comprising the steps of:

(a) generating a circuit layout of said integrated circuit, comprising the substeps of;

(a1) determining a surface area of a layer of metallization used in said circuit;

(a2) comparing said surface area with a first predetermined value;

if said area is less than said first predetermined value, proceeding with the following series of steps;

(a3) initializing a mesh pattern of local wires with physical wires;

(a4) removing an overlap between said local and said physical wires;

(a5) removing portions of said local wires which are within a first predetermined distance from said physical wires;

(a6) removing segments of said local wires of a length less than a second predetermined value;

(a7) creating a boundary of a second predetermined distance surrounding said physical wires; and

(a8) removing segments of said local wires which are outside said boundary;

(b) forming a metallization layer over the chip;

(c) forming a photoresist layer over the metallization layer;

(d) imaging the photoresist layer in accordance with said circuit layout;

(e) developing the photoresist layer;

(f) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and

(g) removing the photoresist layer.

17. A method as in claim 16, in which step (a) further comprises the substeps of:

(a9) changing the characterization of said local wires causing said local wires to appear as physical wires; and

(a10) repeating steps (a1) through (a8) until said area is greater than said first predetermined value.

18. A method as in claim 17, in which step (a) further comprises the substep of:

(a11) distinguishing said local wires from said physical wires;

wherein step (a11) follows said step (a8).