Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus

• US 5,477,475 A
• Filed: 07/11/1994
• Issued: 12/19/1995
• Est. Priority Date: 12/02/1988
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Sample, Stephen P., D'Amour, Michael R., Payne, Thomas S.
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/273,513
• Time in Patent Office: 526 Days
• Field of Search: 364/578, 364/579, 364/580, 364/DIG. 1, 364/232.3, 364/DIG. 2, 364/927.81, 371/16.2, 371/22.1, 371/22.3, 371/23, 371/27, 340/825.22, 340/825.06, 340/825.88, 340/825.89, 340/825.83, 340/825.84, 307/465, 307/468, 307/219, 307/303, 357/45, 395/500, 365/201
• US Class Current: 716/104
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user'"'"'s circuit or system. a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Claims

1. A method for emulating a circuit design in an electrically reconfigurable hardware emulation apparatus, the circuit design characterized by functional circuit components with circuit connections therebetween, the emulation apparatus including electrically reconfigurable devices with reprogrammable functional logic elements capable of performing the functions of the circuit components in the circuit design, the emulation apparatus also including reprogrammable electrically conductive paths capable of reconfigurably interconnecting selected electrically reconfigurable devices such that functional logic elements in one of the selected electrically reconfigurable devices can be electrically coupled to functional logic elements in another of the selected electrically reconfigurable devices, said method comprising the steps of:

electronically generating a netlist description of the circuit components and circuit connections in the circuit design;

partitioning said netlist description by algorithmically assigning the circuit components in said netlist description to partitions which respectively correspond to the selected electrically reconfigurable devices;

routing said partitioned netlist description among the selected electrically reconfigurable devices by algorithmically assigning reprogrammable electrically conductive paths to interconnect the selected electrically reconfigurable devices so as to complete the circuit connections between the circuit components in said netlist description; and

generating configuration information which programs functional logic elements in the selected electrically reconfigurable devices and reprogrammable electrically conductive paths to implement the circuit component functions and circuit connections of the circuit design as partitioned and routed in said partitioning and routing steps.

2. An emulation method as set forth in claim 1, wherein said step of electronically generating a netlist description includes the further steps of:

creating a library file containing information about the characteristics of the circuit components in the circuit design;

creating a schematics data file representing the circuit design;

converting said schematics data file into a netlist file; and

linking the contents of said netlist file with said information from said library file to form a gate level netlist.

3. An emulation method as set forth in claim 1, wherein said contents of said netlist file are first read by a netlist parser and then hierarchically expanded before being linked with said information from said library file.

4. An emulation method as set forth in claim 1, wherein the electrically reconfigurable hardware emulation apparatus further includes fixed resources in the form of external I/O connections, VSLI connections and connections to memory devices, and said step of partitioning said netlist description includes the further step of algorithmically assigning the fixed resources to at least one of said partitions.

5. An emulation method as set forth in claim 1, wherein said step of partitioning said netlist description includes the further steps of:

dividing the circuit components in said netlist description into bins; and

iteratively continuing said step of dividing until the number of said bins equals the number of said partitions which respectively correspond to the selected electrically reconfigurable devices.

6. An emulation method as set forth in claim 4, wherein said step of dividing includes the further steps of:

establishing a threshold number for circuit connections traversing the boundary of a bin;

determining a cutset size for each bin, which cutset size equals the actual number of circuit connections traversing the boundary of said bin;

comparing said cutset size for each bin with said threshold number; and

moving selected circuit components from bins with a cutset size exceeding said threshold to bins with a cutset size which does not exceed said threshold.

7. An emulation method as set forth in claim 1, including the further step of performing a timing analysis with said configuration information prior to implementing the circuit component functions and circuit connections of the circuit design in the selected electrically reconfigurable devices and reprogrammable electrically conductive paths.

8. An emulation method as set forth in claim 1, wherein the functional logic elements in the electrically reconfigurable devices are programmed by serial data input into the electrically reconfigurable devices, said step of generating configuration information including the further steps of:

providing said configuration information in the form of data bytes; and

converting said data bytes into a serial data stream which is directed to the electrically reconfigurable devices containing the functional logic elements to be programmed.

9. An emulation method as set forth in claim 7, wherein the electrically reconfigurable devices have provisions for receiving strobe signals and clock signals in addition to serial data for programming the functional logic elements, said emulation method including the further steps of:

generating address information identifying selected electrically reconfigurable devices containing functional logic elements to be programmed;

generating strobe signals which respectively enable the electrically reconfigurable devices identified by said address information to receive said serial data stream; and

generating clocking signals which clock successive portions of said serial data stream into respective electrically reconfigurable devices identified by said address information.