Semiconductor memory having a high speed sense amplifier

• US 5,477,484 A
• Filed: 12/01/1994
• Issued: 12/19/1995
• Est. Priority Date: 12/01/1993
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakashima, Yasuhiro
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/353,203
• Time in Patent Office: 383 Days
• Field of Search: 365/182, 365/189.01, 365/207, 365/230.06
• US Class Current: 365/182
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A semiconductor memory comprises a memory cell array including a plurality of digit lines, a plurality of word lines, a plurality of memory cells located at intersections between the digit lines and the word lines, and a column selection circuit for selecting one digit line from the digit lines in accordance with a selection signal. A sense amplifier includes a first P-MOS transistor for precharging a digit line selected by the column selection circuit, an inverting amplifier having an input connected to receive a signal on the selected digit line, and a second P-MOS transistor having a gate and a drain connected to an output and an input of the inverting amplifier, respectively. A gate-grounded third P-MOS transistor maintained in a conductive condition is connected at its source to a voltage supply voltage and at its drain connected to a source of the P-MOS second transistor. The third P-MOS transistor has an on-resistance larger than that of the second transistor and substantially the same current driving capability as that of the second transistor.

Claims

1. A semiconductor memory comprising:

a memory cell array 10 including a plurality of digit lines, a plurality of word lines isolated from the plurality of digit lines and intersecting the plurality of digit lines, a plurality of memory cells located at intersections between the plurality of digit lines and the plurality of word lines, each of the memory cells being connected at its one end to a corresponding digit line and at its other end to a reference voltage point, and constructed to store binary information by whether or not the memory cell is conductive between the one end and the other end of the memory cell when a corresponding word line is at a selection level;

a column selection circuit for selecting one digit line from the plurality of digit lines in accordance with a selection signal; and

a sense amplifier including a first transistor for precharging a digit line selected by the column selection circuit, to a predetermined potential at a predetermined timing in response to a precharge signal, an inverting amplifier having an input connected to receive a signal on the selected digit line, for outputting an inverted signal of the received signal, and a second transistor having a gate connected to an output of the inverting amplifier and a drain connected to an input of the inverting amplifier so that the second transistor cooperates with the inverting amplifier so as to maintain a signal level on each of the input and the output of the inverting amplifier, a third transistor having a source connected to a predetermined voltage and a drain connected to a source of the second transistor, the third transistor being maintained in a conductive condition, the third transistor having an on-resistance larger than that of the second transistor and substantially the same current driving capability as that of the second transistor, so that the above mentioned predetermined voltage is transmitted to the source of the second transistor.

2. A semiconductor memory claimed in claim 1 wherein a gate of said third transistor is biased to a predetermined fixed voltage.

3. A semiconductor memory claimed in claim 1 wherein said second and third transistors are of a P-channel field effect transistor, and a gate of said third transistor is biased to a ground potential level.

4. A semiconductor memory claimed in claim 1 wherein said sense amplifier also includes a fourth transistor having a source connected to the predetermined voltage and a drain and agate connected in common to a constant current source, the gate of said fourth transistor being connected to a gate of said third transistor, so that a current mirror circuit is constituted by said third and fourth transistors so as to control an electric current flowing through the third transistor.

5. A semiconductor memory claimed in claim 4 wherein said second, third and fourth transistors are of a P-channel field effect transistor.

6. A semiconductor memory comprising:

a memory cell array including a plurality of digit lines, a plurality of word lines, a plurality of memory cells located at intersections between said digit lines and said word lines;

a column selection circuit coupled to said memory cell array, for selecting one digit line from the digit lines in accordance with a selection signal; and

a sense amplifier including a first transistor having a main current path connected between a voltage supply voltage and a digit line selected by said column selection circuit, said first transistor having a control electrode receiving a precharge signal for precharging said digit line selected by said column selection circuit, an inverting amplifier having an input connected to a connection node between said first transistor and the selected digit line, and a second transistor having a control electrode connected to an output of said inverting amplifier, one end of a main current path of said second transistor being connected to said input of said inverting amplifier, a third transistor maintained in a conductive condition, one end of a main current path of said third transistor being connected to the other end of said main current path of said second transistor, the other end of said man current path of said third transistor being connected to said voltage supply voltage, said third transistor having an on-resistance larger than that of said second transistor and substantially the same current driving capability as that of said second transistor.

7. A semiconductor memory claimed in claim 6 wherein a control electrode of said third transistor is biased to a predetermined fixed voltage.

8. A semiconductor memory claimed in claim 6 wherein said second and third transistors are of a P-channel field effect transistor, and a gate of said third transistor is biased to a ground potential level.

9. A semiconductor memory claimed in claim 6 wherein said sense amplifier also includes a fourth transistor having a main current path one end of which is connected to said voltage supply voltage, and a control electrode and the other end of said main current path of said fourth transistor being in common through a constant current source to ground, said control electrode of said fourth transistor being connected to a control electrode of said third transistor, so that a current mirror circuit is constituted by said third and fourth transistors so as to control an electric current flowing through said third transistor.

10. A semiconductor memory claimed in claim 9 wherein said second, third and fourth transistors are of a P-channel field effect transistor.