High-stability CMOS multi-port register file memory cell with column isolation and current-mirror row line driver
First Claim
1. A multi-port memory comprising:
- a read row line for activating a row of memory cells; and
a memory cell in said row of memory cells comprising;
bistable storage means, having two stable states, for storing a bit of data;
write means for changing from a first of said two stable states to a second of said two stable states of said bistable storage means;
read port means for reading which of said two stable states is stored in said bistable storage means, said read port means comprising;
differential read means for gating a read current in response to said bistable storage means, said differential read means isolating said bistable storage means from said read current wherein said read current is prevented from disturbing said bit of data stored in said bistable storage means; and
read switch means, receiving said read current from said differential read means, for switching said read current to a current sink in response to said read row line, said read switch means isolating said read current from said read row line,whereby said read current flows through said differential read means and said read switch means to said current sink, but said read current is isolated from said bistable storage means and said read row line.
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Abstract
A memory cell has the read current from the bit lines isolated from the bistable storage latch in the cell. Internal nodes of the bistable storage latch control isolated gates of MOS read transistors which gate the read current from the bit lines to a local node within the memory cell. The read current is then switched to ground from the local node by a read switch transistor. The read switch transistor is gated by the read row line. The read current is isolated from the read row line because the read row line is only connected to the isolated gate of the read switch transistor. The read current is also isolated from the bistable storage latch since the read transistors are connected at their isolated MOS gates to the bistable'"'"'s nodes. This isolation of the read current allows additional read ports to be added without disrupting the cell'"'"'s stability or write performance. The read ports are optimized independently of the bistable stability and write performance and even optimized independently of other read ports. For allowing better control of the read currents, a current-mirroring row driver causes the current in the row driver to be mirrored by the read currents flowing through the read switch transistors.
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Citations
21 Claims
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1. A multi-port memory comprising:
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a read row line for activating a row of memory cells; and a memory cell in said row of memory cells comprising; bistable storage means, having two stable states, for storing a bit of data; write means for changing from a first of said two stable states to a second of said two stable states of said bistable storage means; read port means for reading which of said two stable states is stored in said bistable storage means, said read port means comprising; differential read means for gating a read current in response to said bistable storage means, said differential read means isolating said bistable storage means from said read current wherein said read current is prevented from disturbing said bit of data stored in said bistable storage means; and read switch means, receiving said read current from said differential read means, for switching said read current to a current sink in response to said read row line, said read switch means isolating said read current from said read row line, whereby said read current flows through said differential read means and said read switch means to said current sink, but said read current is isolated from said bistable storage means and said read row line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A multi-port memory comprising:
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a write row line for selecting a row of memory cells for writing; write bit lines for transmitting a bit of data to a memory cell for writing to said memory cell; a read row line for activating said row of memory cells for reading to a first read port; a first pair of read bit lines for transmitting said bit of data in said memory cell for sensing by a sense amplifier for said first read port; said memory cell in said row of memory cells comprising; storage means for storing said bit of data, said storage means having a first internal node and a complement internal node; write pass transistors, coupled to conduct current between said write bit lines and in response to said write row line; a local node within said memory cell, said local node separate from said first internal node and said complement internal node; isolated read transistors, having isolated control gates coupled to said first internal node and said complement internal node, for conducting a read current from said first pair of read bit lines to said local node; a read switch transistor, for switching said read current from said local node to a current sink in response to said read row line, said read switch transistor having an isolated control gate coupled to said read row line; wherein said read current is supplied from one of said first pair of read bit lines when said read row line is in an active state, said bit of data determining which read bit line of said first pair of read bit lines will supply said read current, said sense amplifier sensing which read bit line of said first pair of read bit lines supplies said read current and outputting said bit of data in response. - View Dependent Claims (21)
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Specification