High-stability CMOS multi-port register file memory cell with column isolation and current-mirror row line driver

• US 5,477,489 A
• Filed: 03/20/1995
• Issued: 12/19/1995
• Est. Priority Date: 03/20/1995
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Exponential Technology, Inc.
• Inventors: Wiedmann, Siegfried
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): DINH, SON T
• Application Number:
  US08/407,505
• Time in Patent Office: 274 Days
• Field of Search: 365/189.04, 365/230.05, 365/230.06, 365/154
• US Class Current: 365/189.04
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory cell has the read current from the bit lines isolated from the bistable storage latch in the cell. Internal nodes of the bistable storage latch control isolated gates of MOS read transistors which gate the read current from the bit lines to a local node within the memory cell. The read current is then switched to ground from the local node by a read switch transistor. The read switch transistor is gated by the read row line. The read current is isolated from the read row line because the read row line is only connected to the isolated gate of the read switch transistor. The read current is also isolated from the bistable storage latch since the read transistors are connected at their isolated MOS gates to the bistable'"'"'s nodes. This isolation of the read current allows additional read ports to be added without disrupting the cell'"'"'s stability or write performance. The read ports are optimized independently of the bistable stability and write performance and even optimized independently of other read ports. For allowing better control of the read currents, a current-mirroring row driver causes the current in the row driver to be mirrored by the read currents flowing through the read switch transistors.

Claims

1. A multi-port memory comprising:

a read row line for activating a row of memory cells; and

a memory cell in said row of memory cells comprising;

bistable storage means, having two stable states, for storing a bit of data;

write means for changing from a first of said two stable states to a second of said two stable states of said bistable storage means;

read port means for reading which of said two stable states is stored in said bistable storage means, said read port means comprising;

differential read means for gating a read current in response to said bistable storage means, said differential read means isolating said bistable storage means from said read current wherein said read current is prevented from disturbing said bit of data stored in said bistable storage means; and

read switch means, receiving said read current from said differential read means, for switching said read current to a current sink in response to said read row line, said read switch means isolating said read current from said read row line,

whereby said read current flows through said differential read means and said read switch means to said current sink, but said read current is isolated from said bistable storage means and said read row line.

2. The multi-port memory of claim 1 wherein said read current flows through a first substrate channel electrically isolated from said bistable storage means by a first gate oxide, and wherein said read current flows through a second substrate channel electrically isolated from said read row line by a second gate oxide.

3. The multi-port memory of claim 2 wherein said first substrate channel and said first gate oxide comprise a first MOS transistor, and wherein said second substrate channel and said second gate oxide comprise a second MOS transistor.

4. The multi-port memory of claim 3 wherein said differential read means comprises said first MOS transistor and a third MOS transistor, a gate of said first MOS transistor coupled to a first internal node of said bistable storage means and a gate of said third MOS transistor coupled to a second internal node of said bistable storage means, said first and second internal nodes having opposite logic states.

5. The multi-port memory of claim 4 further comprising a first and a second read bit line, said first read bit line coupled to said first substrate channel of said first MOS transistor, said second read bit line coupled to a third substrate channel of said third MOS transistor, said first and second read bit lines biased at a voltage to allow conduction through either said first substrate channel or said third substrate channel in response to said bistable storage means when said read row line is activates said row of memory cells.

6. The multi-port memory of claim 5 wherein said read switch means comprises said second MOS transistor, said read row line connected to a gate of said second MOS transistor, said second substrate channel of said second MOS transistor having a source end of said second channel connected to a current sink and a drain end of said second channel coupled to said first MOS transistor and said third MOS transistor.

7. The multi-port memory of claim 6 wherein a local node connects said drain end of said second channel of said second MOS transistor and source ends of said first substrate channel of said first MOS transistor and said third substrate channel of said third MOS transistor, said local node being within said memory cell.

8. The multi-port memory of claim 6 wherein said current sink is a ground line.

9. The multi-port memory of claim 6 wherein said current sink is an active current sink.

10. The multi-port memory of claim 6 further comprising:

a row driver for driving a voltage on said read row line, said row driver comprising;

a switchable current source for supplying a row driver current in response to a row select signal, said switchable current source coupled to said row line;

a saturation transistor having a gate and a drain coupled to said row line, for sinking said row driver current to ground, said row driver current fixing a voltage of said row line;

whereby Said row driver current flowing through said saturation transistor is mirrored to determine said read current flowing through said read switch means.

11. The multi-port memory of claim 10 wherein said switchable current source comprises a p-channel MOS transistor.

12. The multi-port memory of claim 7 wherein said first, second, and third MOS transistors are n-channel MOS transistors.

13. The multi-port memory of claim 1 further comprising:

a second read row line for activating a second read port to said row of memory cells;

a second read port means for reading which of said two stable states is stored in said bistable storage means, said second read port means comprising;

second differential read means for gating a second read current in response to said bistable storage means, said second differential read means isolating said bistable storage means from said second read current wherein said second read current is prevented from disturbing said bit of data stored in said bistable storage means; and

second read switch means, receiving said second read current from said second differential read means, for switching said second read current to a current sink in response to said second read row line, said second read switch means isolating said second read current from said read row line,

whereby said second read port means and said read port means can both access said bistable storage means.

14. The multi-port memory of claim 13 wherein said second differential read means comprises a fourth MOS transistor and a fifth MOS transistor, a gate of said fourth MOS transistor coupled to said first internal node of said bistable storage means and a gate of said fifth MOS transistor coupled to said second internal node of said bistable storage means, said second read current flowing through a substrate channel of either said fourth MOS transistor or said fifth MOS transistor, said second read current isolated from said bistable storage means by a gate oxide.

15. The multi-port memory of claim 14 wherein said second read switch comprises a sixth MOS transistor, said second read current flowing through a substrate channel in said sixth MOS transistor, electrically isolated from said read row line by a gate oxide of said sixth MOS transistor.

16. The multi-port memory of claim 15 wherein said read current and said second read current have substantially different values, and wherein said read port means has a first access time to read said bit of data in said bistable storage means, said second read port means having a second access time to read said bit of data in said bistable storage means, wherein said first access time is substantially different from said second access time.

17. The multi-port memory of claim 16 wherein said read port means is coupled to a first stage in a pipelined processor having a first requirement for said first access time, and wherein said second read port means is coupled to a second stage in a pipelined processor having a second requirement for said second access time, said first requirement being substantially different from said second requirement.

18. The multi-port memory of claim 13 wherein said bistable storage means comprises a pair of cross-coupled CMOS inverters.

19. The multi-port memory of claim 13 wherein said bistable storage means comprises a pair of cross-coupled inverters, each inverter of said pair of cross-coupled inverters having an n-channel pull-down MOS transistor and a pull-up resistor.

20. A multi-port memory comprising:

a write row line for selecting a row of memory cells for writing;

write bit lines for transmitting a bit of data to a memory cell for writing to said memory cell;

a read row line for activating said row of memory cells for reading to a first read port;

a first pair of read bit lines for transmitting said bit of data in said memory cell for sensing by a sense amplifier for said first read port;

said memory cell in said row of memory cells comprising;

storage means for storing said bit of data, said storage means having a first internal node and a complement internal node;

write pass transistors, coupled to conduct current between said write bit lines and in response to said write row line;

a local node within said memory cell, said local node separate from said first internal node and said complement internal node;

isolated read transistors, having isolated control gates coupled to said first internal node and said complement internal node, for conducting a read current from said first pair of read bit lines to said local node;

a read switch transistor, for switching said read current from said local node to a current sink in response to said read row line, said read switch transistor having an isolated control gate coupled to said read row line;

wherein said read current is supplied from one of said first pair of read bit lines when said read row line is in an active state, said bit of data determining which read bit line of said first pair of read bit lines will supply said read current, said sense amplifier sensing which read bit line of said first pair of read bit lines supplies said read current and outputting said bit of data in response.

21. The multi-port memory of claim 20 further comprising:

a second read row line for activating said row of memory cells for reading to a second read port;

a second pair of read bit lines for transmitting said bit of data in said memory cell for sensing by a second sense amplifier for said second read port;

said memory cell in said row of memory cells further comprising;

a second local node within said memory cell, said second local node separate from said first internal node and said complement internal node and said local node;

second isolated read transistors, having isolated control gates coupled to said first internal node and said complement internal node, for conducting a second read current from said second pair of read bit lines to said second local node;

a second read switch transistor, for switching said second read current from said second local node to said current sink in response to said second read row line, said second read switch transistor having an isolated control gate coupled to said second read row line;

wherein said second read current is supplied from one of said second pair of second read bit lines when said second read row line is in an active state, said bit of data determining which read bit line of said second pair of read bit lines will supply said second read current, said second sense amplifier sensing which read bit line of said second pair of read bit lines supplies said second read current and outputting said bit of data in response,

whereby two read ports and one write port may access said memory cell.