Addressing technique for storing and referencing packet data

• US 5,477,541 A
• Filed: 12/13/1993
• Issued: 12/19/1995
• Est. Priority Date: 09/29/1989
• Status: Expired due to Term

• Current Assignee: Motorola Mobility LLC (Lenovo Group Ltd.)
• Original Assignee: Dale R. Buchholz, Hungkun J. Chang, John M. Kaczmarczyk, Lisa B. Johanson, Michael P. Nolan, Richard E. White, Thomas A. Freeburg
• Inventors: Buchholz, Dale R., Nolan, Michael P., Kaczmarczyk, John M., Chang, Hungkun J., Johanson, Lisa B., White, Richard E., Freeburg, Thomas A.
• Primary Examiner(s): Kizou, Hassan
• Application Number:
  US08/165,789
• Time in Patent Office: 736 Days
• Field of Search: 370/60, 370/60.1, 370/94.1, 370/94.2, 370/94.3, 370/95.1, 370/95.3, 370/92, 370/93, 370/110.1, 370/85.13, 370/85.15, 340/825.52, 455/54.1, 455/33.1, 379/58, 379/59, 379/63, 395/200, 395/250, 395/275, 395/325, 364/251.5, 364/251.6, 364/251.7, 371/48
• US Class Current: 370/392
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• CPC Class Codes: H04L 12/56 Packet switching systems
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04L 12/6402 Hybrid switching fabrics
• CPC Class Codes: H04W 52/0245 according to signal strength
• CPC Class Codes: H04W 92/02 Inter-networking arrangements
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A hierarchical addressing technique is employed in a packet communications system to enhance flexibility in storing and referencing packet information. This method permits packet message data and certain packet control data to be stored in memory locations without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets received or to be transmitted.

Claims

1. A method of processing packets for storage in a communications system memory device, each packet comprising a header having a circuit identification (ID) field, a packet length field, an address type field, an address length field, an address field, a frame-check sequence field and an information field, the method comprising the steps of:

using the circuit ID field content of a packet as a pointer into a plurality of memory registers that hold control information for a plurality of virtual circuits;

accessing the memory register corresponding to the content of the circuit ID field, said memory register further comprising a size field;

comparing the content of the packet length field to the content of the size field in the accessed memory register; and

determining whether the packet'"'"'s information field content will be stored, based on the comparison.

2. The method of claim 1 further including the steps of:

using the address type field content of the packet as a pointer into a plurality of memory address registers;

accessing the address register corresponding to the content of the address type field to read from that memory address register'"'"'s content a number of bytes specified by the content of the address length field of the packet;

comparing the bytes read from the accessed memory address register'"'"'s content against the packet'"'"'s address field content; and

determining whether the packet'"'"'s information field content will be stored, based on the comparison.

3. The method of claim 2 further including the steps of:

performing an error check on the packet header, said error check including the frame check sequence field; and

determining whether to store the content of the information field based on the error check results.

4. The method of claim 3 wherein the information field comprises voice and data information.

5. The method of claim 1 having a packet bit transmission rate of 40 Mbps.

6. The method of claim 5 wherein the circuit ID field comprises 8 bits.

7. The method of claim 6 wherein the packet length field comprises 16 bits.

8. The method of claim 7 wherein the address type field comprises 4 bits.

9. The method of claim 8 wherein the address length field comprises 4 bits.

10. The method of claim 9 wherein the address field comprises a maximum of 128 bits.

11. In an information system in which data is communicated using packets, each packet having a control data portion and a message data portion, a packet communication method comprising the steps of:

storing said message data portion of a packet in a first memory;

storing at least some of said control data portion of the packet in a second memory; and

defining where in the first memory the message data portion of the packet is stored using a hierarchical addressing protocol, said hierarchical addressing protocol including a control block, responsive to storage of the at least some of the control data portion of the packet, for indexing a first packet descriptor said first packet descriptor for further indexing a first buffer descriptor, said first buffer descriptor for further indexing a buffer in the first memory where the message data portion of the packet is stored.

12. The method according to claim 11 wherein said hierarchical addressing protocol further comprises the step of said first packet descriptor indexing a second packet descriptor, said second packet descriptor indexing the first packet descriptor to form a ring thereby linking said first and said second packet descriptors.

13. The method according to claim 12 wherein said first and second packet descriptors index first and second buffer descriptors, respectively in order to define a series of buffers where the message data portion of the packet are stored.

14. The method according to claim 12 further comprising the step of said first packet descriptor indexing a third packet descriptor, said third packet descriptor indexing the first packet descriptor to link said first and said third packet descriptors to form a different ring and define where the message data portion of the packet is stored.

15. The method according to claim 11 further comprising the steps of:

the first buffer descriptor indexing a second buffer descriptor; and

the second buffer descriptor indexing a second buffer in the first memory where the message data portion of the packet is stored.

16. The method according to claim 11 further comprising the step of storing the message data portion of a frequently communicated packet in predetermined locations in the first memory.