Method of making an electronic device having an integrated inductor

• US 5,478,773 A
• Filed: 05/26/1995
• Issued: 12/26/1995
• Est. Priority Date: 04/28/1994
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Dow, Stephen, Maass, Eric C., Marlin, Bill
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/451,866
• Time in Patent Office: 214 Days
• Field of Search: 437/230, 437/198, 437/60, 336/200, 257/531
• US Class Current: 438/381
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An electronic device (10) comprises a copper integrated inductor (11) overlying other solid state components (31) of the device (10). Preferably, the copper inductor (11) is formed of plated copper to a thickness of several microns. The preferred integrated inductor (11) provides significant advantage over external inductors of the past with respect to simplicity of manufacture as well as system size and cost. Additionally, the preferred inductor (11) provides improved inductance per area, lower series resistance and higher Q values, relative to inductors of the past.

Claims

1. A method of making an electronic device comprising:

providing a device substrate;

forming a solid state device in the device substrate;

forming an interconnect layer overlying the solid state device, the interconnect layer having interconnects;

forming a dielectric layer over the interconnect layer;

sputtering a sputtered titanium tungsten layer over the dielectric layer;

sputtering a sputtered copper layer over the sputtered titanium tungsten layer;

plating a plated copper layer over the sputtered copper layer; and

forming a planar integrated inductor from the plated copper layer, the sputtered copper layer, and the sputtered titanium tungsten layer by concurrently etching the plated copper layer at a first rate and the sputtered copper layer at a second rate to expose the sputtered titanium tungsten layer, wherein the first rate is less than the second rate, and by etching the sputtered titanium tungsten layer.

2. The method according to claim 1, further using ammonium peroxydisulfate for concurrently etching the plated copper layer and the sputtered copper layer.

3. The method according to claim 1, further forming the planar integrated inductor overlying the solid state device.

4. The method according to claim 1, further using the interconnect layer for electrically coupling the planar integrated inductor to the solid state device.

5. The method according to claim 1, further providing polyimide for the dielectric layer.

6. The method according to claim 1, further providing aluminum for the interconnect layer.

7. A method of making an electronic device comprising:

providing a substrate having a semiconductor device;

depositing a dielectric layer over the substrate;

providing a metal layer over the dielectric layer;

providing a first copper layer over the metal layer;

patterning a photoresist layer over a first portion of the first copper layer while exposing a second portion of the first copper layer;

providing a second copper layer over the second portion of the first copper layer;

`etching the first copper layer at a first rate while etching the second copper layer at a second rate, wherein the first rate is greater than the second rate; and

etching the metal layer, wherein etching the first copper layer and etching the metal layer defines a passive component.

8. The method according to claim 7, further providing polyimide for the dielectric layer, titanium tungsten for the metal layer, sputtered copper for the first copper layer, and plated copper for the second copper layer.

9. The method according to claim 7, further providing ammonium peroxydisulfate for etching the first copper layer while etching the second copper layer.

10. The method according to claim 7, further providing a planar spiral inductor for the passive component.

11. The method according to claim 7, further defining the passive component over the semiconductor device.

12. The method according to claim 7, further electrically coupling the passive component to the semiconductor device.

13. The method according to claim 7, further providing a protective layer over the second copper layer.

14. A method of making an electronic device having an inductor, comprising:

providing a semiconductor substrate;

forming a semiconductor device in the semiconductor substrate;

providing a copper diffusion barrier over the semiconductor substrate;

`depositing a sputtered copper layer over the copper diffusion barrier;

patterning a plated copper layer over a first portion of the sputtered copper layer while leaving a second portion of the sputtered copper layer exposed;

concurrently etching the second portion of the sputtered copper layer at a first rate while etching the plated copper layer at a second rate to expose a portion of the copper diffusion barrier, wherein the first rate is greater than the second rate; and

etching the portion of the copper diffusion barrier, wherein an inductor is defined by etching the second portion of the sputtered copper layer and etching the portion of the copper diffusion barrier.

15. The method according to claim 14, further providing ammonium peroxydisulfate for concurrently etching the second portion of the sputtered copper layer while etching the plated copper layer.

16. The method according to claim 14, further providing the inductor overlaying the semiconductor device and electrically coupling the inductor and the semiconductor device.

17. The method according to claim 14, further providing titanium tungsten for the copper diffusion barrier.