Polyimide-insulated cube package of stacked semiconductor device chips

• US 5,478,781 A
• Filed: 10/27/1994
• Issued: 12/26/1995
• Est. Priority Date: 06/21/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Miller, Christopher P., Perlman, David J., Howell, Wayne J., Farrar, Paul A. Sr.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/329,954
• Time in Patent Office: 425 Days
• Field of Search: 437/209, 437/210, 437/211, 437/212, 437/213, 437/214, 437/215, 437/216, 437/217, 437/218, 437/219, 437/220
• US Class Current: 438/109
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

Claims

1. A method for forming a semiconductor structure, comprising the steps of:

forming a plurality of integrated circuit chips on an upper surface of a wafer, said wafer having a first coefficient of thermal expansion;

forming a sandwich structure of a first insulation layer, a first layer of transfer metallurgy, and a second insulation layer on said wafer, said first and second layers of insulation having coefficients of thermal expansion that approximate that of said wafer and having dielectric constants no greater than approximately 4;

applying a polymer adhesion material on top of said sandwich structure;

drying said polymer adhesion material without full curing;

dicing said wafer to separate said plurality of integrated circuit chips from one another; and

stacking said plurality of integrated circuit chips together and bonding said stacked chips together by heating to a temperature sufficient to cause said polymer adhesion material to cure.

2. The method as recited in claim 1, wherein said first and second layers of insulation have a glass transition temperature of above approximately 150°

C.

3. The method as recited in claim 1, wherein said first and second layers of insulation have a glass transition temperature of above approximately 350°

C.

4. The method as recited in claim 1, wherein said first and second layers of insulation have a Young'"'"'s Modulus of less than approximately 160 GPa measured along a first given plane of said first and second layers of insulation as formed.

5. The method as recited in claim 4, wherein said first and second layers of insulation have a Young'"'"'s Modulus of less than approximately 10 GPa measured along a second given plane of said first and second layers of insulation as formed, said second given plane being orthogonal to said first given plane.

6. The method as recited in claim 1, wherein said first and second layers of insulation have the same coefficient of thermal expansion.

7. The method as recited in claim 6, wherein said coefficient of thermal expansion is less than approximately 50 ppm/°

C. measured along a first given plane of said first and second layers of insulation as formed.

8. The method as recited in claim 7, wherein said coefficient of thermal expansion is less than approximately 200 ppm/°

C. measured along a second given plane of said first and second layers of insulation as formed, said second given plane being orthogonal to said first given plane.

9. The method as recited in claim 1, wherein both of said first and second layers of insulation have dielectric constants of approximately 3.6.

10. The method as recited in claim 9, wherein said dielectric constants are substantially similar in all planes.

11. The method as recited in claim 10, wherein said first and second layers of insulation are comprised of BPDA-PDA.

12. The method as recited in claim 1, further comprising the steps of

depositing a layer of polyimide on an exposed surface of the plurality of integrated circuit chips as bonded together;

and

depositing a layer of interconnect metallurgy that contacts said first layer of transfer metallurgy through said layer of polyimide.

13. The method as recited in claim 12, wherein said layer of polyimide is comprised of BPDA-PDA.

14. The method as recited in claim 1, wherein said step of forming said sandwich structure further comprises the steps of:

depositing a first layer of polyimide on said wafer, and drying said first layer of polyimide without producing full imidization;

depositing said layer of transfer metallurgy that extends through said first layer of polyimide to contact conductive portions of said integrated circuits on said plurality of integrated circuit chips; and

depositing a second layer of polyimide on said wafer, and fully curing both of said first and second layers of polyimide.

15. A method of forming a multi-chip integrated circuit structure, comprising the steps of:

forming a plurality of integrated circuit chips on a wafer, said wafer having a first coefficient of thermal expansion, each of said plurality of integrated circuit chips having a first passivation layer thereon;

forming an interconnection structure on said first passivation layer, comprising a first layer of metal disposed within a first polymer material, said first polymer material having a coefficient of thermal expansion that approximates that of said wafer and a dielectric constant that is less than approximately 4;

forming an adhesive polymer layer on said interconnection structure, said adhesive polyimide layer being heated to stabilize without fully curing;

dicing said plurality of integrated circuit chips from said wafer;

bonding at least one of said plurality of integrated circuit chips to another one of said plurality of integrated circuit chips by bringing a surface of one of said plurality of integrated circuit chips into contact with a surface of another one of said plurality of integrated circuit chips having said layer of adhesive polymer layer thereon, and fully curing said adhesive polymer layer to form a unitized multi-chip body having a plurality of surfaces;

depositing a second passivation layer on one of said plurality of surfaces of said unitized body; and

forming a second layer of metal that extends through said second passivation layer to contact said first layer of metal.

16. The method of claim 15, wherein during said step of forming said plurality of integrated circuit chips on said wafer, said first passivation layer is etched to form an edge surface, such that during said dicing step said first passivation layer is not cut.

17. The method of claim 16, wherein said first polymer material is disposed over said edge surface of said first passivation layer, such that during said dicing step said first polymer material is cut.

18. A method of bonding a first integrated circuit chip to a workpiece, of said first integrated circuit chip being diced from a wafer having a plurality of integrated circuit chip images on a first surface thereon including said first integrated circuit chip image, comprising the steps of

depositing a polymer layer on a first surface of said wafer;

drying said polymer layer;

dicing said wafer;

bringing said polymer layer on said first integrated circuit chip into contact with said workpiece; and

fully curing said polymer layer.

19. The method of claim 18, further comprising the step of:

prior to said step of depositing said polymer adhesive layer, thinning said wafer by removing a portion of a second surface of said wafer opposite said first surface.

20. The method of claim 18, further comprising the steps of:

prior to said step of dicing said wafer, depositing a protective layer on said polymer layer; and

after said step of dicing said wafer, removing said protective layer.

21. The method of claim 20, wherein said protective layer comprises photoresist.

22. The method of claim 18, further comprising the step of, after said step of dicing said wafer, removing a surface portion of said polymer layer.

23. The method of claim 18, further comprising the steps of:

after said step of fully curing said polymer layer,

bonding the first integrated circuit chip and said workpiece to a carrier, said carrier being comprised of a first material, said polymer material having a coefficient of thermal expansion that is similar to that of said first material.

24. The method of claim 23, wherein said first material is comprised of ceramic or glass.

25. A method for forming a semiconductor structure comprising the steps of:

a) forming a plurality of integrated circuit chips on a wafer, each of said plurality of integrated circuit chips having a first passivation layer thereon;

b) forming a sandwich structure on said first passivation layer, said structure comprising a first polymeric insulation layer, a first rerouting metal layer and a second polymeric insulation layer;

c) dicing said plurality of integrated circuit chips from said wafer;

d) bonding at least one of said plurality of integrated circuit chips to another chip to form a unitized multi-chip body having a plurality of surfaces;

e) depositing a second passivation layer on one of said plurality of surfaces of said unitized body; and

f) forming a second layer of metal that extends through said second passivation layer to contact said first rerouting metal layer.

26. A method as recited in claim 25, wherein said second layer of metal extends over said second passivation layer.

27. A method as recited in claim 25, wherein said wafer, said first, and said second polymeric insulation layers have coefficients of thermal expansion that are approximately equal.

28. A method as recited in claim 25, wherein said first polymeric insulation layer has a dielectric constant that is less than approximately 4.

29. A method as recited in claim 25, further comprising between said steps (b) and (c) the step of forming an adhesive layer on said second polymeric insulation layer.

30. A method as recited in claim 29, wherein said adhesive is polymeric.

31. A method as recited in claim 30, wherein said first and second polymeric layers and said adhesive are polyimides.

32. A method as recited in claim 31, wherein said polyimides include one of BPDA-PDA, Dupont 5878, PMDA-ODA and Thermid.

33. A method as recited in claim 30, further comprising the step of heating to stabilize said polymeric adhesive without substantial curing and wherein said bonding step (d) is accomplished by bringing a surface of one of said plurality of integrated circuit chips into contact with a surface of another chip, said adhesive polymer layer therebetween, and fully curing said adhesive polymer layer.

34. A method as recited in claim 25, further comprising between said steps (b) and (c) the step of heating to stabilize said second polymeric insulation layer without curing, and wherein said bonding step (d) is accomplished by bringing a surface of one of said plurality of integrated circuit chips into contact with a surface of another chip, said second polymeric insulation layer therebetween, and fully cuing said second polymeric insulation layer.

35. The method as recited in claim 25, wherein during said step of forming said plurality of integrated circuit chips on said wafer, said first passivation layer is etched to form an edge surface, such that during said dicing step said first passivation layer is not cut.

36. The method as recited in of claim 35, wherein said first polymer material is disposed over said edge surface of said first passivation layer, such that during said dicing step said first polymer material is cut.