Testing device for integrated circuits on wafer

• US 5,479,109 A
• Filed: 01/28/1994
• Issued: 12/26/1995
• Est. Priority Date: 06/03/1992
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Lui, Kenneth, Lau, James C. K., Malmgren, Richard P.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US08/187,952
• Time in Patent Office: 697 Days
• Field of Search: 324/757, 324/758, 324/750, 324/763, 324/762, 324/763, 324/754, 348/87, 356/401, 439/482
• US Class Current: 324/750.18
• CPC Class Codes: G01R 1/07357 with flexible bodies, e.g. buckling beams

Abstract

An electrical testing device is provided for testing integrated circuits located on a wafer. The testing device employs a multi-layer test circuit having a plurality of contacts for contacting the integrated circuits on a wafer. The layers of the test circuit are embedded in a flexible transparent dielectric material which allows vertical flexing of the contacts and visual transparency through the circuit. Alignment markers are provided on the circuit and wafer and one or more viewing tubes may be used to allow a user to view the alignment markers so as to bring the circuit into proper alignment with the wafer. A microscope may further be employed with each viewing tube to provide accurate alignment examination. A stretching fixture is mounted on the circuit which enables a user to stretch the circuit to achieve a larger size when necessary.

Claims

1. An electrical testing device for testing integrated circuits on a wafer, said device comprising:

circuit means including a multilayer test circuit fabricated in a flexible dielectric material and having a plurality of conductive contacts extending from a contact surface thereof for contacting contact points connected to circuitry on the wafer to be tested;

stretching means for selectively stretching said circuit means so as to expand the contact surface of the test circuit to compensate for misalignment between the conductive contacts and contact points;

actuation means for forcibly causing the conductive contacts to contact the contact points on the wafer;

a first set of alignment markers located within said multilayer test circuit, said first set of alignment markers being operable for aligning with a second set of alignment markers located on a top surface of said wafer; and

viewing means for allowing visual viewing through the dielectric material of the test circuit and the first and second sets of alignment markers so that the first set of alignment markers may be aligned with the second set of alignment markers to achieve alignment of the conductive contacts with the contact points on the wafer.

2. The device as defined in claim 1 wherein said stretching means comprises first and second spaced rings located on one side of the circuit means and a third ring located on the other side, wherein said third ring is forcibly moved toward the first and second rings so as to compress the dielectric material therebetween thereby causing the circuit to expand.

3. The device as defined in claim 1 further comprising a dimensionally stable and transparent support material located on top of the circuit means.

4. The device as defined in claim 1 wherein said viewing means comprises at least one viewing tube.

5. The device as defined in claim 1 wherein said viewing means comprises at least one microscope.

6. The device as defined in claim 1 wherein said dielectric material comprises a transparent material.

7. An electrical testing device for testing integrated circuits on a wafer, said device comprising:

circuit means including a multilayer test circuit fabricated in a flexible and transparent dielectric material and having a plurality of conductive contacts extending from a contact surface for contacting contact points connected to circuitry on the wafer;

actuation means for forcibly causing the conductive contacts to come into contact with the contact points on the wafer;

alignment means for visually aligning the circuit means with the wafer so that the conductive contacts are aligned with the integrated circuit on the wafer; and

stretching means for selectively stretching the circuit means so as to expand the contact surface of the test circuit to compensate for misalignment of the conductive contacts and contact points.

8. The device as defined in claim 7 wherein said stretching means comprises first and second spaced rings located on one side of the circuit means and a third ring located on the other side, wherein said third ring is forcibly moved toward the first and second rings so as to compress the dielectric material therebetween thereby causing the circuit to expand to a desired shape.

9. The device as defined in claim 7 wherein said alignment means comprises one or more viewing tubes.

10. The device as defined in claim 7 wherein said alignment means comprises one or more microscopes.

11. The device as defined in claim 7 wherein said alignment means further includes a first set of alignment markers located within the multilayer test circuit, said first set of alignment markers being operable for aligning with a second set of alignment markers located on a top surface of the wafer, wherein a user may visually look through the transparent material of the test circuit and align the first set of alignment markers with the second set of alignment markers to bring the conductive contacts into alignment with the contact points on the wafer.

12. An electrical testing device for testing integrated circuits on a wafer, said device comprising:

circuit means including a thin multilayer test circuit fabricated in a flexible and transparent dielectric material and having a plurality of conductive contacts extending from a contact surface for contacting contact points connected to circuitry on the wafer to be tested;

actuation means for forcibly causing the conductive contacts to contact the contact points on the wafer;

a first set of alignment markers located within the multilayer test circuit;

a second set of alignment markers located on the wafer;

viewing means for allowing visually viewing through the transparent dielectric material of the test circuit and the first and second sets of alignment markers so that the first set of alignment markers may be aligned with the second set of alignment markers so as to bring the conductive contacts into alignment with the contact points on the wafer; and

stretching means including a plurality of compressible rings for stretching the circuit means when necessary to enlarge the contact surface of the test circuit so as to compensate for misalignment between the conductive contacts and contact points.

13. A method of testing electrical integrated circuits on a wafer comprising:

loading a wafer to be tested onto a base support structure;

forcibly actuating a test circuit which is embedded in a flexible and transparent dielectric material and which has a plurality of conductive contacts extending from a contact surface so as to bring the conductive contacts into contact with contact points connected to integrated circuitry on the water;

visually aligning the conductive contacts with the integrated circuitry on the wafer by looking through the transparent dielectric material of the test circuit and viewing alignment markers through at least one viewing region looking through the circuit;

stretching the test circuit and the dielectric material when necessary to expand the contact surface of the test circuit so that the contacts match the arrangement of contact points on the wafer; and

testing said integrated circuits by applying and receiving signals via selected ones of the contacts.

14. The method as defined in claim 13 wherein said step of visually aligning includes viewing said alignment markers through a microscope located in each viewing region.