High speed sampler and demultiplexer

• US 5,479,120 A
• Filed: 05/11/1994
• Issued: 12/26/1995
• Est. Priority Date: 09/08/1992
• Status: Expired due to Term

• Current Assignee: Lawrence Livermore National Security LLC (Government of the United States of America)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: McEwan, Thomas E.
• Primary Examiner(s): Dolinar, Andrew M.
• Application Number:
  US08/241,000
• Time in Patent Office: 594 Days
• Field of Search: 327/91, 327/94, 327/415, 327/92, 324/76.15
• US Class Current: 327/91
• CPC Class Codes: G01R 19/0053 Noise discrimination; Analog sampling; Measuring transients measuring characteristics of individual pulses G01R29/02; digital sampling G01R19/2509; measuring noise figure G01R29/26
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

A high speed sampling demultiplexer based on a plurality of sampler banks, each bank comprising a sample transmission line for transmitting an input signal, a strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates at respective positions along the sample transmission line for sampling the input signal in response to the strobe signal. Strobe control circuitry is coupled to the plurality of banks, and supplies a sequence of bank strobe signals to the strobe transmission lines in each of the plurality of banks, and includes circuits for controlling the timing of the bank strobe signals among the banks of samplers. Input circuitry is included for supplying the input signal to be sampled to the plurality of sample transmission lines in the respective banks. The strobe control circuitry can repetitively strobe the plurality of banks of samplers such that the banks of samplers are cycled to create a long sample length. Second tier demultiplexing circuitry is coupled to each of the samplers in the plurality of banks. The second tier demultiplexing circuitry senses the sample taken by the corresponding sampler each time the bank in which the sampler is found is strobed. A plurality of such samples can be stored by the second tier demultiplexing circuitry for later processing. Repetitive sampling with the high speed transient sampler induces an effect known as "strobe kickout". The sample transmission lines include structures which reduce strobe kickout to acceptable levels, generally 60 dB below the signal, by absorbing the kickout pulses before the next sampling repetition.

Claims

1. A high speed sampler, comprising:

a plurality of sampler banks, each bank including

a sample transmission line for transmitting a bank input signal;

a strobe transmission line for transmitting a bank strobe signal; and

sampler circuitry, connected to the strobe transmission line and the sample transmission line at a plurality of positions, which samples the bank input signal at the plurality of positions in response to the bank strobe signal to supply a plurality of samples of the input signal with a first effective sampling rate;

strobe control circuitry, coupled with the plurality of sampler banks,

which supplies a sequence of bank strobe signals to the strobe transmission lines in each of the plurality of banks, including circuits for controlling timing of the bank strobe signals;

input circuitry, coupled with the plurality of sampler banks, which supplies an input signal to the sample transmission lines in each of the plurality of banks; and

second tier demultiplexing circuitry coupled to the sampler circuitry in the plurality of positions which senses each of a plurality of samples to store samples developed in response to a plurality of strobe signals from each position for later processing.

2. The high speed sampler of claim 1, wherein the second tier demultiplexing circuitry comprises a plurality of sets of sample and hold circuits, each set holding a plurality of samples from a given position in the sampling circuitry.

3. The high speed sampler of claim 1, wherein the second tier demultiplexing circuitry comprises a plurality of analog to digital converters coupled to respective positions in the plurality of positions in the sampling circuitry, and digital memory coupled to the analog to digital converters, each analog to digital converter converting a plurality of samples from a given position in the sampling circuitry.

4. The high speed sampler of claim 1, wherein the input circuitry comprises a signal splitter with high reverse attenuation.

5. The high speed sampler of claim 1, wherein the sample transmission line in a particular sampler bank has a proximal end coupled to the input circuitry and a distal end, and including a broadband termination resistor on the distal end of the sample transmission line.

6. The high speed sampler of claim 1, wherein the sample transmission lines in the plurality of sampler banks have respective proximal ends coupled to the input circuitry and respective distal ends, and wherein the input circuitry comprises a passive resistive splitter coupled to the proximal ends, and broadband termination resistors on the distal ends providing transmission line terminations which suppress strobe kickout on the respective sample transmission lines.

7. The high speed sampler of claim 1, wherein the sample transmission lines in the plurality of sampler banks have respective proximal ends coupled to the input circuitry and respective distal ends, and wherein the input circuitry comprises an active splitter coupled to the proximal ends.

8. The high speed sampler of claim 7, including broadband termination resistors on the distal ends, and at the active splitter with the broadband termination resistors providing transmission line terminations which suppress strobe kickout on the respective sample transmission lines.

9. The high speed sampler of claim 8, wherein the active splitter comprises an input transmission line receiving the input signal, and a plurality of high speed drivers coupled to the input transmission line and to respective ones of the sample transmission lines in the plurality of banks, which drive the corresponding bank in response to the input signal on the transmission line.

10. The high speed sampler of claim 9, wherein each of the high speed drivers comprise:

an FET transistor having a gate connected to the input transmission line, and a drain coupled to the sample transmission line of the respective bank, and

an operational amplifier circuit connected between the input transmission line and sample transmission line to control lower frequency signals on the sample transmission line.

11. The high speed sampler of claim 1, wherein the strobe control circuitry includes a trigger signal generator, and a plurality of pulse forming networks coupled to respective strobe transmission lines, and wherein the circuitry for controlling timing comprises a fanout circuit coupled to the trigger signal generator for supplying a trigger signal to each of the plurality of pulse forming networks with controlled timing.

12. The high speed sampler of claim 11, wherein the trigger signal generator comprises an RF power amplifier.

13. The high speed sampler of claim 11, wherein the controlled timing is set with varying lengths of cable between the trigger signal generator and the plurality of pulse forming networks.

14. The high speed sampler of claim 1, wherein the circuitry for controlling timing incrementally delays the bank strobe signals so that the samples in respective pluralities of samples from at least a subset of the plurality of banks are interleaved in time.

15. The high speed sampler of claim 1, wherein the circuitry for controlling timing incrementally delays the bank strobe signals so that the samples in respective pluralities of samples from at least a subset of the plurality of banks are concatenated in time.

16. The high speed sampler of claim 1, wherein the sampler circuitry in at least one bank includes a plurality of diode bridge sample gates connected to the sample transmission line at respective ones of the plurality of positions.

17. A high speed sampler, comprising:

a plurality of sampler banks, each bank including

a sample transmission line for transmitting a bank input signal;

a strobe transmission line for transmitting a bank strobe signal; and

sampler circuitry, connected to the strobe transmission line and the sample transmission line at a plurality of positions, which samples the bank input signal at the plurality of positions in response to the bank strobe signal to supply a plurality of samples of the input signal;

strobe control circuitry, coupled with the plurality of sampler banks, which supplies the bank strobe signals to the strobe transmission lines in each of the plurality of banks, including circuits for controlling timing of the bank strobe signals; and

input circuitry, coupled with the plurality of sampler banks, which supplies an input signal to the sample transmission lines in each of the plurality of banks in parallel, and suppresses strobe kickout.

18. The high speed sampler of claim 17, wherein the input circuitry comprises a signal splitter with high reverse attenuation

19. The high speed sampler of claim 17, wherein the sample transmission line in a particular sampler bank has a proximal end coupled to the input circuitry and a distal end, and including a broadband termination resistor on the distal end of the sample transmission line.

20. The high speed sampler of claim 17, wherein the sample transmission lines in the plurality of sampler banks have respective proximal ends coupled to the input circuitry and respective distal ends, and wherein the input circuitry comprises a passive resistive splitter coupled to the proximal ends, and broadband termination resistors on the distal ends providing transmission line terminations which suppress strobe kickout on the respective sample transmission lines.

21. The high speed sampler of claim 17, wherein the sample transmission lines in the plurality of sampler banks have respective proximal ends coupled to the input circuitry and respective distal ends, and wherein the input circuitry comprises an active splitter coupled to the proximal ends.

22. The high speed sampler of claim 21, including broadband termination resistors on the distal ends, the active splitter and the broadband termination resistors providing transmission line terminations which suppress strobe kickout on the respective sample transmission lines.

23. The high speed sampler of claim 21, wherein the active splitter comprises an input transmission line receiving the input signal, and a plurality of high speed drivers coupled to the input transmission line and to respective ones of the sample transmission lines in the plurality of banks, which drive the corresponding bank in response to the input signal on the transmission line.

24. The high speed sampler of claim 23, wherein each of the high speed drivers comprise:

an FET transistor having a gate connected to the input transmission line, and a drain coupled to the sample transmission line of the respective bank, and

an operational amplifier circuit connected to control lower frequency signals on the sample transmission line.

25. The high speed sampler of claim 17, wherein the strobe control circuitry includes a trigger signal generator, and a plurality of pulse forming networks coupled to respective strobe transmission lines, and wherein the circuitry for controlling timing comprises a fanout circuit coupled to the trigger signal generator for supplying a trigger signal to each of the plurality of pulse forming networks with controlled timing.

26. The high speed sampler of claim 25, wherein the trigger signal generation comprises an RF power amplifier.

27. The high speed sampler of claim 25, wherein the controlled timing is set with varying lengths of cable between the trigger signal generator and the plurality of pulse forming networks.

28. The high speed sampler of claim 17, wherein the circuitry for controlling timing incrementally delays the bank strobe signals so that the samples in respective pluralities of samples from at least a subset of the plurality of banks are interleaved in time.

29. The high speed sampler of claim 17, wherein the circuitry for controlling timing incrementally delays the bank strobe signals so that the samples in respective pluralities of samples from at least a subset of the plurality of banks are concatenated in time.

30. The high speed sampler of claim 17, wherein the sampler circuitry in at least one bank includes a plurality of diode bridge sample gates connected to the sample transmission line at respective ones of the plurality of positions.

31. The high speed sampler of claim 17, further including means, coupled to the sampler circuitry in the plurality of banks, for scanning out the samples from the plurality of banks in coordination with the circuits for controlling timing.