Method and apparatus for long-term multi-valued storage in dynamic analog memory

• US 5,479,170 A
• Filed: 11/02/1993
• Issued: 12/26/1995
• Est. Priority Date: 10/16/1992
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: California Institute of Technology
• Inventors: Cauwenberghs, Gert, Yariv, Amnon
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US08/146,660
• Time in Patent Office: 784 Days
• Field of Search: 341/110, 341/144, 341/200
• US Class Current: 341/200
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 27/00 Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H03M 1/464 Non-linear conversion
• CPC Class Codes: H03M 1/664 Non-linear conversion not otherwise provided for in subgroups of H03M1/66

Abstract

A method and apparatus is described for refreshing the analog content of a analog memory having a volatile storage device. An analog value stored on a volatile storage device is iteratively adjusted to maintain the analog value in proximity to one of a set of predetermined discrete analog memory levels. Binary quantization of the stored value, yielding one bit of information corresponding to the analog value stored, determines whether to increase or decrease the stored value by a given small amount. In essence, the bit obtained by binary quantization encodes the direction toward the nearest discrete level. Memory retention achieved by periodic iteration of the method is robust to noise and random errors in the quantization, over a wide range of operating conditions. The apparatus includes as functional elements a binary quantizer and an increment/decrement refresh device, which may interface with the analog storage means in a variety of configurations, including configurations supporting multiplexed schemes for sharing quantizers and increment/decrement refresh devices among multiple storage cells.

Claims

1. An apparatus comprising:

storage means for storing an analog value; and

refresh means for repeatedly either increasing or decreasing said analog value of said storage means by pre-selected incremental amounts to maintain said analog value near one of a plurality of discrete levels, with said analog value being increased or decreased depending on a determination of the analog value.

2. The apparatus of claim 1, wherein said refresh means comprises

means for generating a binary value assigned to a first state if said analog value is greater than a nearest adjacent discrete level and assigned to a second state, if said analog value is less than said nearest adjacent level;

and

increment/decrement means for increasing said analog value by a first pre-selected amount, if said binary value is in said first state, and for decreasing said analog value by a second pre-selected amount, if said binary value is in said second state.

3. The apparatus of claim 1, wherein said refresh means comprises

binary quantization means for generating a binary value in response to said analog value of said storage means, said binary value being in either a first state or a second state, with the state of said binary value being determined from said analog value in a consistent and substantially repeatable manner;

increment/decrement means for increasing said analog value by a first pre-selected amount, if said binary value is in said first state, and for decreasing said analog value by a second pre-selected amount, if said binary value is in said second state.

4. The apparatus of claim 3, wherein said first and second pre-selected amounts are substantially equal.

5. The apparatus of claim 3, wherein said first and second pre-selected amounts are substantially less than a minimum separation between adjacent predetermined analog levels.

6. The apparatus of claim 3, wherein said first and second pre-selected amounts are greater than r₁ T, wherein r₁ is a leakage drift rate for said storage means and T is a refresh time interval.

7. The apparatus of claim 3, wherein a plurality of said storage means and a plurality of said increment/decrement means are provided, with said quantization means sequentially generating a binary value in response to the analog value of one particular one of said plurality of storage means at a time, and with one of said plurality of increment/decrement means subsequently increasing or decreasing said analog value of said one particular storage means using said binary value from said quantization means.

8. The apparatus of claim 3 or claim 7, wherein said binary quantization means comprises:

a comparator with non-inverting and inverting inputs and non-inverted output, said comparator being operated in a latched comparison mode;

a digital-to-analog converter having a bit-serial digital input connected to said non-inverted output of said comparator and having an analog output connected to said inverting input of said comparator;

with said analog value being supplied to said non-inverting input of said comparator, and with said binary value being obtained from said non-inverted output of said comparator.

9. The apparatus of claim 8, further providing write access to said analog value, said comparator including an inverted output, with said inverted output being active and said comparator being operated in differential amplification mode during a write phase, and with said non-inverted output of said comparator being active and said comparator being operated in latched comparison mode otherwise.

10. The apparatus of claim 9, further including a write switch connected between said inverted output and said non-inverting input of said comparator, said write switch being activated only during said write phase.

11. The apparatus of claim 8, wherein said digital-to-analog converter comprises:

first and second charge holding means each capable of holding an electric charge;

switching means coupled to said first and second charge holding means, said switching means when activated electrically coupling said first and second charge holding means for sharing and redistributing the charge contained by said first and second charge holding means with approximately equal charge density;

third and fourth charge holding means each capable of holding an electric charge;

a first bi-directional replication element coupled between said first charge holding means and said third charge holding means, said first bi-directional replication element having a store mode and a recall mode of operation, said first bi-directional replication element establishing a charge on said third charge holding means corresponding to the charge stored on said first charge holding means determined by a first transfer function when said first bi-directional replication element is operated in store mode, said first bi-directional replication element establishing a charge on said first charge holding means corresponding to the charge stored on said third charge holding means determined by a second transfer function when said first bi-directional replication element is operated in recall mode; and

a second bi-directional replication element coupled between said second charge holding means and said fourth charge holding means, said second bi-directional replication element having a store mode and a recall mode of operation, said second bi-directional replication element establishing a charge on said fourth charge holding means corresponding to the charge stored on said second charge holding means determined by a third transfer function when said second bi-directional replication element is operated in store mode, said second bi-directional replication element establishing a charge on said second charge holding means corresponding to the charge stored on said fourth charge holding means determined by a fourth transfer function when said second bi-directional replication element is operated in recall mode,

with said analog output of said digital-to-analog converter being obtained from the charge contained by either said first or second charge holding means, and with said bit-serial digital input of said digital-to-analog converter determining said store and recall operations of said first and second bi-directional replication elements sequentially.

12. The apparatus of claim 3 or claim 7, wherein said means for storing an analog value is a capacitor and wherein said increment/decrement means comprises:

a NOR-gate having a first input receiving a first control signal and a second input receiving a second control signal;

a NAND-gate having a first input receiving a complement for said first control signal and a second input receiving said second control signal;

a pMOS transistor having a source connected to an output of said NOR-gate, a gate connected to a first constant bias voltage, and a drain connected to an output node; and

an nMOS transistor having a source connected to an output of said NAND-gate, a gate connected to a second constant bias voltage and a drain connected to said output node.

13. The apparatus of claim 1, further including means for externally accessing and altering said analog value on said storage means.

14. The apparatus of claim 1, wherein a plurality of said storage means are provided with said refresh means sequentially refreshing one of said plurality of storage means at a time.

15. An apparatus for repeatedly refreshing an analog value stored in a storage means, said apparatus comprising:

binary quantization means for repeatedly generating a binary value in response to said analog value stored in said storage means, said binary value being either a first or a second state; and

increment/decrement means, responsive to each binary value, for increasing said analog value by a first pre-select amount, if said binary value is in said first state, and for decreasing said analog value by a second pre-selected amount, if said binary value is in said second state;

with

the state of said binary value generated by said quantization means being determined from said analog value in a consistent and substantially repeatable manner.

16. The apparatus of claim 15, wherein said first and second pre-selected amounts are substantially equal.

17. The apparatus of claim 15, wherein a plurality of said storage means and a plurality of said increment/decrement means are provided, with said quantization means sequentially generating a binary value in response to the analog value of one particular one of said plurality of storage means at a time, and with one of said plurality of increment/decrement means subsequently increasing or decreasing said analog value of said one particular storage means using said binary value from said quantization means.

18. The apparatus of claim 15 or claim 17, wherein said binary quantization means comprises:

a comparator with non-inverting and inverting inputs and non-inverted output, said comparator being operated in a latch comparison mode;

a digital-to-analog converter having a bit-serial digital input connected to said non-inverted output of said comparator and having an analog output connected to said inverting input of said comparator;

with said analog value being supplied to said non-inverting input of said comparator, and with said binary value being obtained from said non-inverted output of said comparator.

19. The apparatus of claim 18, further providing write access to said analog value, said comparator including an inverted output, with said inverted output being active and said comparator being operated in differential amplification mode during a write phase, and with said non-inverted output of said comparator being active and said comparator being operated in latched comparison mode otherwise.

20. The apparatus of claim 19, further including a write switch connected between said inverted output and said non-inverting input of said comparator, said write switch being activated only during said write phase.

21. The apparatus of claim 18, wherein said digital-to-analog converter comprises:

first and second charge holding means each capable of holding an electric charge;

switching means coupled to said first and second charge holding means, said switching means when activated electrically coupling said first and second charge holding means for sharing and redistributing the charge contained by said first and second charge holding means with approximately equal charge density;

third and fourth charge holding means each capable of holding an electric charge;

a first bi-directional replication element coupled between said first charge holding means and said third charge holding means, said first bi-directional replication element having a store mode and a recall mode of operation, said first bi-directional replication element establishing a charge on said third charge holding means corresponding to the charge stored on said first charge holding means determined by a first transfer function when said first bi-directional replication element is operated in store mode, said first bi-directional replication element establishing a charge on said first charge holding means corresponding to the charge stored on said third charge holding means determined by a second transfer function when said first bi-directional replication element is operated in recall mode; and

a second bi-directional replication element coupled between said second charge holding means and said fourth charge holding means, said second bi-directional replication element having a store mode and a recall mode of operation, said second bi-directional replication element establishing a charge on said fourth charge holding means corresponding to the charge stored on said second charge holding means determined by a third transfer function when said second bi-directional replication element is operated in store mode, said second bi-directional replication element establishing a charge on said second charge holding means corresponding to the charge stored on said fourth charge holding means determined by a fourth transfer function when said second hi-directional replication element is operated in recall mode,

with said analog output of said digital-to-analog converter being obtained from the charge contained by either said first or second charge holding means, and with said bit-serial digital input of said digital-to-analog converter determining said store and recall operations of said first and second bi-directional replication elements sequentially.

22. The apparatus of claim 15 or claim 17, wherein the analog storage means is a capacitor and wherein said increment/decrement means comprises:

a NOR-gate having a first input receiving a first control signal and a second input receiving a second control signal;

a NAND-gate having a first input receiving said first control signal inverted and a second input receiving said second control signal;

a pMOS transistor having a source connected to an output of said NOR-gate, a gate connected to a first constant bias voltage, and a drain connected to an output node; and

an nMOS transistor having a source connected to an output of said NAND-gate, a gate connected to a second constant bias voltage and a drain connected to said output node.

23. In an analog multi-valued memory comprising analog storage means, an apparatus for refreshing the analog value on said analog storage means defining the state of said analog multi-valued memory comprising:

means for obtaining a binary quantization value corresponding to said analog value, said binary quantization value being in either a first or a second state; and

means for increasing said analog value by a first fixed amount, if said binary quantization value is in said first state, and for decreasing said analog value by a second fixed amount, if said binary quantization value is in said second state.

24. The apparatus of claim 23, wherein said means for generating a binary quantization value and the means for increasing or decreasing the analog value are operated repeatedly to maintain said analog value near a predetermined analog level.

25. The apparatus of claim 23, wherein said binary value is assigned to said first state if said analog value is below a nearest predetermined analog level and wherein said binary value is assigned to said second state if said analog value is greater than said nearest predetermined analog level.

26. A method for maintaining an analog value near one of a plurality of discrete levels, said method comprising repeating the step of:

either increasing or decreasing said analog value by pre-selected amounts, with said analog value being increased or decreased depending on said analog value.

27. The method of claim 26, wherein said step further comprises the steps of:

generating a binary value assigned to a first state if said analog value is greater than a nearest adjacent discrete level and assigned to a second state, if said analog value is less than said nearest adjacent level; and

increasing said analog value by a first pre-selected amount, if said binary value is in said first state, and decreasing said analog value by a second pre-selected amount, if said binary value is in said second state.

28. The method of claim 26, wherein said step further comprises the steps of:

generating a binary value in response to said analog value, said binary value being in either a first state or a second state, with the state of said binary value being determined from said analog value in a consistent and substantially repeatable manner; and

increasing said analog value by a first pre-selected amount, if said binary value is in said first state, and decreasing said analog value by a second pre-selected amount, if said binary value is in said second state.

29. The method of claim 28, wherein said first and second pre-selected amounts are substantially equal.

30. The method of claim 28, wherein said first and second pre-selected amounts are substantially less than a minimum separation between adjacent said predetermined analog levels.

31. The method of claim 28, wherein said first and second pre-selected amounts are greater than r₁ T, wherein r₁ is a leakage drift rate for said storage means and T is a refresh time interval.

32. A method for refreshing an analog value stored in an analog value storage means, said method comprising the steps of:

generating a binary value in response to an analog value stored in the analog storage means, said binary value being in either a first state or a second state, with the state of said binary value being determined from said analog value in a consistent and substantially repeatable manner; and

increasing said analog value by a first pre-selected amount, if said binary value is in said first state, and decreasing said analog value by a second pre-selected amount, if said binary value is in said second state.

33. The method of claim 32, wherein said first and second pre-selected amounts are substantially equal.

34. In an analog multi-valued memory comprising analog storage means, the method of refreshing the analog value on said analog storage means defining the state of said analog multi-valued memory comprising the steps of:

obtaining a binary quantization value corresponding to said analog value, said binary quantization value being in either a first or a second state;

increasing said analog value by a first fixed amount, if said binary value is in said first state; and

decreasing said analog value by a second fixed amount, if said binary quantization value is in said second state.

35. The apparatus of claim 34, wherein said steps of generating a binary quantization value and increasing or decreasing the analog value are performed repeatedly to maintain said analog value near a predetermined analog level.

36. The method of claim 34, wherein said binary value is assigned to said first state if said analog value is below a nearest predetermined analog level and wherein said binary value is assigned to said second state if said analog value is greater than said nearest predetermined analog level.