Spacer flash cell device with vertically oriented floating gate

• US 5,479,368 A
• Filed: 09/30/1993
• Issued: 12/26/1995
• Est. Priority Date: 09/30/1993
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Keshtbod, Parviz
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/129,866
• Time in Patent Office: 817 Days
• Field of Search: 365/185, 257/315, 257/316, 257/319, 257/320, 257/321, 257/324, 257/326, 257/318
• US Class Current: 365/185.3
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed. A gate oxide is grown and a second polysilicon layer is formed and then etched to form spacers along the edges of the first polysilicon/second insulator structure. The second polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A third polysilicon layer is formed over the tunneling insulator.

Claims

1. A nonvolatile memory cell comprising:

a. a planar substrate of a semiconductor material having an upper surface and further having a conductive source region and a conductive drain region formed in the upper surface having a channel region therebetween;

b. a floating gate that is coupled to the substrate, wherein the floating gate is formed of a conductive material that is surrounded by an electrically insulating material and further wherein the floating gate has a cross section which is longer along one axis than it is along its other axis, the floating gate having at least one surface parallel to the longer axis that is substantially perpendicular to the substrate, the floating gate having a sharp tip at an end of the surface furthest from the substrate wherein the floating gate is positioned over and electrically controls only a portion of the channel adjacent the drain; and

c. a control gate, coupled to the substrate so that the floating gate is between the control gate and the substrate, wherein the control gate is spaced apart from the floating gate by the insulating material such that the control gate only overlaps a portion of the floating gate along the at least one surface parallel to the longer axis that is substantially perpendicular to the substrate furthest from the substrate and only comes into close proximity with the floating gate in this region of overlap wherein the control gate is positioned over the channel and electrically controls only that portion of the channel not controlled by the floating gate, such that the channel is split into two portions wherein a first portion of the channel is controlled by the floating gate and a second portion of the channel is controlled by the control gate and further wherein the floating gate is programmed by hot electron injection from a weakly conducting second portion.

2. The memory cell according to claim 1 wherein the cell is electrically erasable.

3. The memory cell according to claim 2 wherein the cell is erased through the insulating material where the control gate comes into close proximity with the sharp tip of the floating gate.

4. The memory cell according to claim 1 wherein the substrate is formed of single crystal silicon.

5. The memory cell according to claim 1 wherein the floating gate is formed of doped polysilicon.

6. The memory cell according to claim 1 wherein the control gate is formed of doped polysilicon.

7. The memory cell according to claim 1 wherein the insulating material is formed of Si₃ N₄ along a portion of the surface of the floating gate that is substantially perpendicular to the substrate and formed of SiO₂ elsewhere.

8. The memory cell according to claim 1 wherein the distance between the floating gate and the control gate in the region of the sharp tip of the spacer overlap is approximately 200 Å

and approximately 1000 Å

elsewhere.

9. A nonvolatile memory cell comprising:

a. a planar substrate of a semiconductor material having a surface, wherein the substrate is doped to a first conductivity type having a drain region and a source region space apart from one another and formed within the surface forming a channel therebetween;

b. a first conductive material having at least one planar first sidewall substantially perpendicular to the substrate, wherein the first conductive material is formed over the drain region and spaced apart from the drain by a first insulating layer wherein the first insulating layer includes a substantially planar second insulating layer along the first sidewall that is coupled to the first insulating layer;

c. a second conductive material having a substantially planar second sidewall, wherein the second conductive material is formed over the substrate and adjacent to the first conductive material and between the drain and the source regions but spaced apart from the source region such that the second sidewall is coupled to the second insulating layer and further wherein the second conductive material is surrounded by a third insulating layer and wherein the second conductive material extends further from the substrate than the first conductive material leaving an exposed and insulated portion of the second sidewall wherein the second conductive material covers and electrically controls only a portion of the channel adjacent the drain; and

d. a third conductive material formed over the substrate and extending from the source region to the drain region such that the second conductive material is between the third conductive material and the substrate such that the third conductive material is spaced apart from the second conductive material by a first distance along a surface of the second conductive material away from the substrate and the second sidewall and a second distance along the exposed and insulated portion of the second sidewall wherein the second distance is less than the first distance wherein the third conductive material covers the channel but only electrically controls that portion of the channel not covered by the second conductive material, such that the channel is split into two portions wherein a first portion of the channel is controlled by the second conductive material and

a second portion of the channel is controlled by the third conductive material

and further wherein the second conductive material receives electrons through hot electron injection from a weakly conducting second portion.

10. The memory cell according to claim 9, wherein the first conductive material is doped polysilicon, the second conductive material is doped polysilicon and the third conductive material is doped polysilicon.

11. The memory cell according to claim 9 wherein the first conductive material is electrically coupled to the drain.

12. The memory cell according to claim 9 wherein the first insulating layer and the second insulating layer are formed of Si₃ N₄.

13. The memory cell according to claim 9 wherein the third insulating layer is SiO₂.

14. The memory cell according to claim 9 wherein the first distance is approximately 1000 Å

and the second distance is approximately 200 Å

.

15. The memory cell according to claim 9 wherein a capacitive coupling between the first conductive material and the second conductive material is approximately 0.75 and the capacitive coupling between the second conductive material and the third conductive material is approximately 0.15.

16. The memory cell according to claim 9 wherein the cell cannot over erase.