Semiconductor memory device employing sense amplifier control circuit and word line control circuit

• US 5,479,374 A
• Filed: 07/25/1994
• Issued: 12/26/1995
• Est. Priority Date: 05/27/1992
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kobayashi, Tsuguo, Nogami, Kazutaka, Shirotori, Tsukasa
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/279,684
• Time in Patent Office: 519 Days
• Field of Search: 365/233.5, 365/233, 365/202, 365/203, 365/154, 365/156, 365/190, 365/205, 365/206, 365/207, 365/226, 365/227, 365/189.05, 365/230.03, 307/530, 327/51
• US Class Current: 365/233.5
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor memory device capable of reducing power consumption has a memory cell array, a plurality of address lines, a pair of data lines, an address transition detector circuit for outputting an address transition signal in response to a change in a signal on the address line, a sense amplifier, a sense amplifier control circuit for activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal, and a word line control circuit which deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.

Claims

1. A semiconductor memory device comprising:

a memory cell array having a plurality of word lines for accessing data stored within the memory cell array;

a plurality of address lines coupled to the memory cell array so as to designate a memory cell within the memory cell array;

a pair of data lines coupled to the memory cell within the memory cell array for acquiring complementary data from the memory cell;

an address transition detector circuit coupled to the address lines to output an address transition signal in response to a change in a signal on the address lines;

an equalizer circuit coupled to the pair of data lines and responsive to the address transition signal to establish a signal having the same predetermined value on each of the pair of data lines;

a sense amplifier coupled to the pair of data lines for generating a sense amplifier output signal in response to a change in potential on the pair of the data lines;

a sense amplifier control circuit coupled to the address transition detector circuit and coupled to the sense amplifier, the sense amplifier control circuit activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal; and

a word line control circuit coupled to the sense amplifier control circuit and to the memory cell array, wherein the word line control circuit deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.

2. The semiconductor memory device of claim 1 further comprising a decoder coupled to the address lines and to the word line control circuit, wherein the word line control circuit causes the decoder to disable the word lines in response to a signal generated by the sense amplifier control circuit.

3. The semiconductor memory device of claim 1 wherein the sense amplifier output signal comprises a pair of digital signals and wherein one of the digital signals becomes the logical complement of the other of the digital signals when data are present on the pair of data lines when the sense amplifier is activated and wherein the one of the digital signals becomes the same as the other of the digital signals when the sense amplifier is deactivated.

4. The semiconductor memory device of claim 3 wherein the sense amplifier control circuit deactivates the sense amplifier in response to one of the digital signals becoming different from the other of the digital signals.

5. The semiconductor memory device of claim 1 wherein the sense amplifier control circuit generates a sense amplifier control signal in response to the address transition signal and the sense amplifier output signal, wherein one value of the sense amplifier control signal activates the sense amplifier and wherein a second value of the sense amplifier control signal deactivates the sense amplifier.

6. The semiconductor memory device of claim 5 wherein the second value of the sense amplifier control signal causes the word line control circuit to deactivate the word lines in the memory cell array.

7. A semiconductor memory device comprising:

a memory cell array having a plurality of word lines for accessing data stored within the memory cell array;

a plurality of address lines coupled to the memory cell array so as to designate a memory cell within the memory cell array;

a pair of data lines coupled to the memory cell within the memory cell array for acquiring complementary data from the memory cell;

an address transition detector circuit coupled to the address lines to output an address transition signal in response to a change in a signal on the address lines;

a sense amplifier coupled to the pair of data lines for generating a sense amplifier output signal in response to a change in potential on the pair of the data lines;

a sense amplifier control circuit coupled to the address transition detector circuit and coupled to the sense amplifier to provide a control signal to the sense amplifier and to receive the sense amplifier output signal, the sense amplifier control circuit activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal; and

a word line control circuit coupled to the sense amplifier control circuit and to the memory cell array, wherein the word line control circuit deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.