Cascaded VLSI neural network architecture for on-line learning

• US 5,479,579 A
• Filed: 09/22/1994
• Issued: 12/26/1995
• Est. Priority Date: 09/04/1992
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
• Original Assignee: United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration
• Inventors: Duong, Tuan A., Daud, Taher, Thakoor, Anilkumar P.
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): Dorvil, Richemond
• Application Number:
  US08/316,711
• Time in Patent Office: 460 Days
• Field of Search: 395/22, 395/24, 395/27
• US Class Current: 706/36
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A computation-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates.

Claims

1. A neuroprocessor comprising at least one synapse chip formed as a matrix of synapse nodes and comprising a plurality of voltage inputs and a plurality of current outputs, each such synapse node comprising a voltage-to-current converter, a two-quadrant multiplying digital-to-analog converter, a plurality of static weighting latches and a current steering circuit;

a synapse-neuron composite chip comprising one said synapse chip in which a diagonal line of synapse nodes within said matrix of synapse nodes is replaced by a plurality of neurons;

a thresholding comparator having a sigmoidal function to input currents, a current-to-voltage converter and a variable-gain voltage amplifier circuit for adjusting said sigmoidal function;

wherein said synapse chip and said synapse-neuron composite chip are connected in a parallel cascaded configuration wherein output current variation of the synapse-neuron composite chip is added to an output current variation of the synapse chip to provide a combined resolution commensurate with a sum of resolutions of both chips.

2. The neuroprocessor as claimed in claim 1 wherein said synapse chip and synapse-neuron composite chip are implemented in VLSI circuits.

3. The neuroprocessor as claimed in claim 1 wherein said synapse-neuron composite chip comprises a modified form of said synapse integrated circuit chip wherein a diagonal line of synapse nodes in said matrix of synapse nodes is replaced with a plurality of neurons in Mid synapse-neuron composite chip.

4. The neuroprocessor as claimed in claim 1 wherein each of said neurons comprises:

a thresholding comparator having a sigmoidal function to input currents, a current-to-voltage converter and a variable gain voltage amplifier circuit for adjusting said sigmoidal function.

5. The neuroprocessor as claimed in claim 1 wherein said synapse-neuron composite chip is configured for full connectivity wherein each neuron therein is connected to every other neuron including itself.