Real-time ring bandwidth utilization calculator, calculating bandwidth utilization based on occurrences of first and second predetermined bit patterns

• US 5,479,613 A
• Filed: 08/05/1992
• Issued: 12/26/1995
• Est. Priority Date: 08/05/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, Joseph K., Geyer, Joel E.
• Primary Examiner(s): Black, Thomas C.
• Assistant Examiner(s): Harrity, Paul
• Application Number:
  US07/926,071
• Time in Patent Office: 1,238 Days
• Field of Search: 395/800, 395/725, 395/325, 395/200, 340/825.5, 370/85.1, 370/85.2, 370/85.3, 370/85.4, 370/85.5, 370/85.6, 370/85.15
• US Class Current: 709/224
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/022 by sampling
• CPC Class Codes: H04L 43/0852 Delays
• CPC Class Codes: H04L 43/0882 Utilisation of link capacity

Abstract

An adapter which attaches Data Terminal Equipment (DTE) to a LAN includes a latch whose state is changed by conditions, such as a free token or a frame, on the LAN. The output of the latch is used to calculate the bandwidth utilization of the LAN.

Claims

1. An improved circuit arrangement for measuring bandwidth utilization in a communications network including a common transmission medium to which at least one Data Terminal Equipment DTE is connected, said circuit arrangement comprising:

a storage means for storing data representative of bandwidth utilization caused by Data Terminal Equipment DTE;

a first circuit means, operatively coupled to the transmission medium, said first circuit means monitoring data transmission on the transmission medium, generating a first control signal which sets the storage means in a first state if a first predetermined bit pattern is detected on said transmission medium and generating a second control signal which sets the storage means in a second state if a second predetermined bit pattern is detected on said transmission medium;

a front end interface means for coupling the storage means and the first circuit means with the transmission medium;

wherein said first circuit means further includes

a data deserializer coupled to the front end interface means;

a code violation CV error detector, coupled to the data deserializer, for detecting code violation;

a Start Delimiter SDEL detector, coupled to the data deserializer, for detecting beginning of a frame;

a clock extraction circuit means, coupled to the front end interface means, for extracting clocking signals from data received from the transmission medium;

a frame SYNC generator coupled to the clock extraction circuit means, for outputting time and byte boundaries signals;

a signal loss detector, coupled to the front end interface means, for detecting absence of signals on the transmission medium; and

a Token Monitor State Machine, responsive to a first set of signals outputted from the SDEL detector, the CV error detector, the data deserializer, the frame SYNC generator and the signal loss detector, for generating the first control signal which sets the storage means to the first state and the second control signal which wets the storage means to the second state; and

controller means for correlating signals representative of the first state and the second state to calculate the bandwidth utilization.

2. The improved circuit arrangement of claim 1 further including a gating circuit means responsive to signals outputted from the signal loss detector and the Token Monitor State Machine to generate the second control signal which includes a Reset signal which resets the storage means.

3. The improved circuit arrangement of claim 2 wherein the gating circuit means includes a logical "OR" circuit.