Method and device for updating information elements in a memory

• US 5,479,637 A
• Filed: 02/25/1993
• Issued: 12/26/1995
• Est. Priority Date: 08/31/1990
• Status: Expired due to Term

• Current Assignee: Gemplus International SA (Thales SA)
• Original Assignee: Gemplus International SA (Thales SA)
• Inventors: Paradinas, Pierre, Lisimaque, Gilles
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Nguyen, Hiep T.
• Application Number:
  US07/984,431
• Time in Patent Office: 1,034 Days
• Field of Search: 395/400, 395/425, 395/430, 395/443, 395/421.09, 235/492, 371/10.1, 371/10.2, 371/10.3
• US Class Current: 711/103
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

A method for updating information elements in a memory which includes a plurality of memory locations. An initial value D0 has been written at a first location E0 of the memory, E0 being determined by an initial value of a string of indicator bits, the initial value being defined by the parity of the rank of a last bit of the string of indicator bits in a programmed state. The method includes: writing a new value D1 at another location E1 of the memory, E1 being determined by the initial value of the string of logic indicator bits; verifying the written value in E1 by comparing the written value in E1 with D1; emitting an error code to a processing unit, if, after verifying the written value in El, the written value in E1 does not match D1; erasing the string of indicator bits entirely so that all of the indicator bits are in a blank state and writing the first bit to the programmed state, if, after verifying the written value in El, i) all the indicator bits are in the programmed state and ii) the written value in E1 matches D1, so as to make the value written in E1 accessible in a reading mode; and writing a first bit of the string of indicator bits in a blank state to the programmed state if, after verifying the written value in E1 and before erasing, i) the value written in E1 matches D1 and ii) all the indicator bits are not in the programmed state, so as to make the value written in E1 accessible in a reading mode. The plurality of memory locations are written serially according to successive updatings.

Claims

1. A method for updating information elements in a memory which includes, for each kind of elements, two memory locations, wherein an initial value D0 of an information element has been written at a first location E0 of the memory of the two locations for that element, E0 being determined by an initial value of a string of indicator bits, the initial value being defined by the parity of the rank of a last bit of the string of indicator bits in a programmed state, the method comprising:

writing a new value D1 at the other location E1 of the memory for that element, E1 being determined by the parity of the rank of a first blank state bit of the string of logic indicator bits;

verifying the written value in E1 by comparing the written value in E1 with D1;

emitting an error code to a processing unit, if, after verifying the written value in E1, the written value in E1 does not match D1; and

writing a bit of the string of indicator bits in a blank state subsequent to said last programmed state bit, to the programmed state if, after verifying the written value in E1, i) the value written in E1 matches D1 and ii) all the indicator bits are not in the programmed state, so as to make the value written in E1 accessible in a reading mode,

wherein locations E0 and E1 are written alternately according to successive updatings.

2. Method according to claim 1, wherein the memory is an erasable re-recordable memory and includes, for each of a plurality of information elements to be updated, a memory location E to which the information element is transferred from E1 after verifying that the written value in E1 matches the value D1.

3. Method according to claim 2, wherein writing the new value D1 includes writing an address A(E) of the memory location E into which the information element will be transferred.

4. Method according to claim 3, wherein a logic indicator b associated with the transference of the information element to E is positioned in a first logic state before writing a new value D1.

5. Method according to claim 2, wherein a logic indicator b associated with the transference of the information element to E is positioned in a first logic state before writing the new value D1.

6. Method according to claim 1, wherein said memory is a memory card.

7. Method according to claim 3, wherein the memory card comprises a microprocessor and the method of updating the information element in the memory is implemented by a software program of the microprocessor of the memory card.

8. The method according to claim 1 further comprising erasing the string of indicator bits entirely so that all of the indicator bits are in a blank state and writing the first bit to the programmed state, if, after verifying the written value in E1, i) all the indicator bits are in the programmed state and ii) the written value in E1 matches D1, so as to make the value written in E1 accessible in a reading mode.

9. A method for updating information elements in a memory which includes a plurality of memory locations, wherein an initial value D0 has been written at a first location E0 of the memory, E0 being determined by an initial value of a string of indicator bits, the initial value being defined by the parity of the rank of a last bit of the string of indicator bits in a programmed state, the method comprising:

writing a new value D1 at another location E1 of the memory, E1 being determined by the first blank state bit parity of the rank of a string of logic indicator bits;

verifying the written value in E1 by comparing the written value in E1 with D1;

emitting an error code to a processing unit, if, after verifying the written value in E1, the written value in E1 does not match D1;

erasing the string of indicator bits entirely so that all of the indicator bits are in a blank state and writing the first bit to the programmed state, if, after verifying the written value in E1, i) all the indicator bits are in the programmed state and ii) the written value in E1 matches D1, and writing a first bit of the string of indicator bits in a blank state to the programmed state, so as to make the value written in E1 accessible in a reading mode.

10. A method according to claim 9, wherein, if, after verifying the written value in E1, i) all the indicator bits are in the programmed state and ii) the written value in E1 matches D1, the method further comprises:

writing a control bit to a control bit first state before erasing the string of indicator bits entirely;

verifying, the complete erasure of the string of indicator bits; and

writing the control bit to a control bit second state.

11. Method according to claim 9, wherein said memory is a memory card.

12. Method according to claim 11, wherein the memory card includes a microprocessor and the method of updating the information element in the memory is implemented by a software program of the microprocessor of the memory card.

13. An updating device for updating information elements comprising:

a memory which includes a plurality of memory locations;

a string of indicator bits;

means for writing an initial value D0 at a first location E0 of the memory;

means for determining the location E0 by an initial value of the string of indicator bits, the initial value being defined by the parity of the rank of a last bit of the string of indicator bits in a programmed state;

means for writing a new value D1 at another location E1 of the memory, the location E1 being determined by the first blank state bit parity of the rank of a of the string of logic indicator bits;

means for verifying the written value in E1 by comparing the written value in E1 with D1;

means for emitting an error code to a processing unit, if, after verifying the written value in E1, the written value in E1 does not match D1;

means for erasing the string of indicator bits entirely so that all of the indicator bits are in a blank state and writing the first bit to the programmed state, if, after verifying the written value in E1, i) all the indicator bits are in the programmed state and ii) the written value in E1 matches D1, so as to make the value written in E1 accessible in a reading mode; and

an automation designed to activate the different steps of the updating of the memory.

14. A device according to claim 13, further comprising a microprocessor connected to the memory,

wherein the automation includes software implemented by the microprocessor connected to the memory.

15. A device according to claim 13, wherein the memory includes control inputs and the automation is a circuit coupled to the control inputs of the memory.

16. A device according to claim 13, wherein the string of indicator bits is a string of logic indicators without indeterminate state, said string of logic indicators being a value of binary elements without indeterminate state such that changing a binary element from the blank state to the programmed state does not effect other binary elements while, conversely, all the binary elements go from the programmed state to the blank state together by simultaneous erasure of the string.

17. An updating device for updating information elements comprising:

a memory which includes a plurality of memory locations;

a string of indicator bits;

means for writing an initial value D0 at a first location E0 of the memory;

means for determining E0 by an initial value of the string of indicator bits, the initial value being defined by the parity of the rank of a last bit of the string of indicator bits in a programmed state;

means for writing a new value D1 at another location E1 of the memory, E1 being determined by the parity of the rank of a of the string of logic indicator bits;

means for verifying the written value in E1 by comparing the written value in E1 with D1;

means for emitting an error code to a processing unit, if, after verifying the written value in E1, the written value in E1 does not match D1;

means for erasing the string of indicator bits entirely so that all of the indicator bits are in a blank state and writing the first bit to the programmed state, if, after verifying the written value in E1, i) all the indicator bits are in the programmed state and ii) the written value in E1 matches D1, so as to make the value written in E1 accessible in a reading mode;

means for writing a first bit of the string of indicator bits in a blank state to the programmed state if, after verifying the written value in E1 and before erasing, i) the value written in E1 matches D1 and ii) all the indicator bits are not in the programmed state, so as to make the value written in E1 accessible in a reading mode; and

an automation designed to activate the different steps of the updating of the memory.

18. A device according to claim 17 further comprising means for transferring the information element from E1 to a memory location E after verifying that the written value in E1 matches the value D1,

wherein the memory is an erasable re-recordable memory and includes, for each of a plurality of information elements to be updated, the memory location E.

19. A device according to claim 18, further comprising a microprocessor connected to the memory,

wherein the automation includes software implemented by the microprocessor connected to the memory.

20. A device according to claim 18, wherein the memory includes control inputs and the automation is a circuit coupled to the control inputs of the memory.

21. A device according to claim 18, wherein the string of indicator bits is a string of logic indicators without indeterminate state, said string of logic indicators being a value of binary elements without indeterminate state such that changing a binary element from the blank state to the programmed state does not effect other binary elements while, conversely, all the binary elements go from the programmed state to the blank state together by simultaneous erasure of the string.

22. A method for updating information elements in a memory which includes a plurality of memory locations, wherein an initial value D0 has been written at a first location E0 of the memory, E0 being determined by an initial value of a string of indicator bits, the initial value being defined by the parity of the rank of a last bit of the string of indicator bits in a programmed state, the method comprising:

writing a new value D1 at another location E1 of the memory, E1 being determined by the parity of rank of a of the string of logic indicator bits;

verifying the written value in E1 by comparing the written value in E1 with D1;

emitting an error code to a processing unit, if, after verifying the written value in E1, the written value in E1 does not match D1;

erasing the string of indicator bits entirely so that all of the indicator bits are in a blank state and writing the first bit to the programmed state, if, after verifying the written value in E1, i) all the indicator bits are in the programmed state and ii) the written value in E1 matches D1, so as to make the value written in E1 accessible in a reading mode; and

writing a first bit of the string of indicator bits in a blank state to the programmed state if, after verifying the written value in E1 and before erasing, i) the value written in E1 matches D1 and ii) all the indicator bits are not in the programmed state, so as to make the value written in E1 accessible in a reading mode,

wherein the plurality of memory locations are written serially according to successive updatings.