Flash memory mass storage architecture incorporation wear leveling technique

• US 5,479,638 A
• Filed: 03/26/1993
• Issued: 12/26/1995
• Est. Priority Date: 03/26/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Estakhri, Petro, Nemazie, Siamack, Assar, Mahmud
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/037,893
• Time in Patent Office: 1,005 Days
• Field of Search: 395/425, 365/900, 365/218, 365/189.07
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system

Abstract

A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoids an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit for evenly using all blocks in the mass storage is provided. These advantages are achieved through the use of several flags, a map to directly correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old version of a block, a count to determine the number of times a block has been erased and written and erase inhibit.

Claims

1. A non-volatile semiconductor mass storage device comprising:

a. a plurality of non-volatile storage blocks, wherein each block is selectively programmable and erasable and only blocks containing no data may be programmed;

b. means for determining whether any unprogrammed blocks remain;

c. means for replacing superseded data with updated data, the means for replacing including nonvolatile flag means, corresponding to each of the storage blocks, and programming means, wherein the nonvolatile flag means is set for blocks having superseded data and further wherein the programming means stores updated data into a block containing no data; and

d. means for periodically and selectively erasing all blocks having nonvolatile flag means which are set, whereby an erase cycle is not needed each time data is stored into one of the blocks;

e. means for correlating coupled to the storage blocks and to the means for replacing for directly correlating a logical address assigned to superseded data to a physical address of updated data wherein the non-volatile flag means and a logical address of each of the storage blocks are stored in a nonvolatile content addressable memory.

2. The device according to claim 1 wherein the means for periodically and selectively erasing simultaneously erases all blocks having non-volatile flag means which are set.

3. The device according to claim 2 wherein the means for periodically and selectively erasing comprises a plurality of nonvolatile single bit storage cells, one cell for and coupled to each storage block, each cell for storing an appropriate used flag and a plurality of volatile latches, one for each cell, coupled to receive a logic state of the cell during an erase cycle.

4. The device according to claim 3 wherein all latches simultaneously receive the logic state of a corresponding cell.

5. The device according to claim 1 further comprising means for ensuring coupled to the storage blocks and to the means for periodically and selectively erasing for ensuring that no block is subjected to more than a predetermined number of erase cycles relative to all other blocks.

6. The device according to claim 5 wherein the means for ensuring comprises a counter for each block for counting each erase cycle to which that block has been subjected.

7. The device according to claim 6 wherein the means for ensuring further comprises means for setting a predetermined maximum count value coupled to each of the storage blocks, and an erase inhibit flag for each of the storage blocks coupled to a counter of a respective storage block, the erase inhibit flag having a set condition and an unset condition for each storage block, for preventing further erases to a block having its erase inhibit flag in the set condition.

8. The device according to claim 7 wherein the counter for each block includes a plurality of bits programmed by binary counting.

9. The device according to claim 7 wherein the counter for each block includes a plurality of bits programmed by sequentially programming each bit, one at a time, wherein each programmed bit represents a count of one.

10. The device according to claim 7 wherein the counter and the erase inhibit flag for each of the storage blocks are stored in the content addressable memory.

11. The device according to claim 7 further comprising a reset means coupled to the means for ensuring for erasing the counter and the erase inhibit flag for each of the storage blocks having an erase inhibit flag in the set condition, wherein the reset means is activated once an insufficient number of storage blocks remain to store a pending data file.

12. The device according to claim 11 further comprising means for reading coupled to the storage blocks comprising:

a. means for receiving a logical address of a data file to be read;

b. means for selecting an appropriate physical address which correlates to the logical address of the data file to be read; and

c. means for accessing the data file to be read from storage blocks corresponding to the appropriate physical address.

13. The device according to claim 12 wherein the means for selecting an appropriate physical address comprises coupling the logical address of a data file to be read to the content addressable memory.

14. A non-volatile semiconductor mass storage device comprising:

a. a plurality of non-volatile storage blocks, wherein each block is selectively programmable and erasable;

b. a first indicating element to provide a first indicia whether each block has been programmed with a data file;

c. a second indicating element to provide a second indicia whether the data file of each programmed block is superseded;

d. a programming element to program a new data file into an empty block; and

e. a periodically activated erasing circuit coupled to each of the storage blocks for selectively erasing all blocks in which the data file is superseded, wherein the erasing circuit is not activated each time data is stored in one of the storage blocks;

f. means for correlating coupled to the storage blocks and to the programming element for directly correlating a logical address assigned to superseded data to a physical address of updated data wherein the first indicating element, the second indicating element and the logical address are stored in a nonvolatile content addressable memory.

15. The device according to claim 14 wherein the erasing circuit, when activated, simultaneously erases all blocks having a superseded data file.

16. The device according to claim 15 wherein the erasing circuit includes a plurality of nonvolatile single bit storage cells, one cell for and coupled to each block, each cell for storing an appropriate second indicia and a plurality of volatile latches, one for each cell, coupled to receive a logic state of the cell during an erase cycle.

17. The device according to claim 16 wherein all latches simultaneously receive the logic state of a corresponding cell.

18. The device according to claim 15 further comprising a first controller coupled to the storage blocks and to the erasing circuit for ensuring that no block is subjected to more than a predetermined number of erase cycles relative to all other blocks.

19. The device according to claim 18 wherein the first controller includes a counter for each block for counting each erase cycle to which that block has been subjected.

20. The device according to claim 19 wherein the counter for each block includes a plurality of bits programmed by binary counting.

21. The device according to claim 19 wherein the counter for each block includes a plurality of bits programmed by sequentially programming each bit, one at a time, wherein each programmed bit represents a count of one.

22. The device according to claim 19 further comprising a second controller to set a maximum count value coupled to the first controller and to each of the storage blocks, and an erase inhibit flag for each storage block coupled to the counter for each block, the erase inhibit flag having a set condition and an unset condition for preventing further erases to a block having its erase inhibit flag in the set condition.

23. The device according to claim 22 wherein the counter and the erase inhibit flag for each of the storage blocks are stored in the content addressable memory.

24. The device according to claim 22 further comprising a reset element coupled to the first controller and to the second controller for erasing all counters, first indicating element, second indicating element and all erase inhibit flags for every block at the maximum count value once insufficient blocks remain to store a pending data file.

25. The device according to claim 24 further comprising a reading element coupled to the storage blocks comprising:

a. a first circuit to receive a logical address of a data file to be read;

b. a second circuit to select an appropriate physical address which correlates to the logical address of the data file to be read; and

c. a third circuit to access the data file to be read from storage blocks corresponding to the appropriate physical address.

26. The device according to claim 25 wherein the second circuit couples the logical address of a data file to be read to the content addressable memory.

27. A non-volatile semiconductor mass storage device comprising:

a. a plurality of non-volatile storage blocks, wherein each block is selectively programmable to store data and is selectively erasable;

b. a plurality of first flags, one first flag for each block, each first flag having a first logic state to indicate that a block has not been programmed with data and a second logic state to indicate that the block has been programmed with data;

c. a selecting element coupled to the storage blocks and to the plurality of first flags for identifying an empty storage block having a first flag in the first logic state where new and updated data may be stored;

d. a plurality of second flags that can only be changed in a block having its first flag in the second logic state, one second flag for each block, each second flag having a third logic state to indicate that the data in a block is valid and a fourth logic state to indicate that the data in the block has been superseded;

e. a content addressable memory for storing a logical address assigned to a block of superseded data and a physical address of a block of updated data corresponding to the superseded data; and

f. an erasing circuit coupled to each of the storage blocks for selectively erasing all blocks having a second flag in the fourth logic state, wherein the erasing circuit is not activated each time data is stored in a storage block; and

g. means for directly correlating coupled to the storage blocks and to content addressable memory, for correlating a logical address assigned to the superseded data to a physical address of updated data.

28. The device according to claim 27 wherein the erasing circuit simultaneously erases each block having a second flag in the fourth logic state.

29. The device according to claim 28 wherein the erasing circuit comprises a plurality of nonvolatile single bit storage cells, one single bit storage cell coupled to each block for storing a corresponding one of the plurality of second flags, and a plurality of volatile latches, each coupled to a respective one of the plurality of single bit storage cells for receiving a logic state of the respective single bit storage cell during an erase cycle.

30. The device according to claim 29 wherein all latches simultaneously receive the logic state of a corresponding cell.

31. The device according to claim 30 wherein the storage blocks store data in flash memory cells.

32. The device according to claim 31 wherein the flags are stored in flash memory cells.

33. The device according to claim 32 wherein the means for correlating are stored in flash memory cells.

34. The device according to claim 30 wherein each of the plurality of storage blocks comprises E² PROM cells.

35. The device according to claim 34 wherein the flags are stored in E² PROM cells.

36. The device according to claim 35 wherein the means for correlating are stored in E² PROM cells.

37. A method of storing data into a non-volatile semiconductor mass storage device having a plurality of non-volatile storage blocks, wherein each block is selectively programmable and erasable wherein only blocks containing no data may be programmed, the method comprising the steps of:

a. determining whether any unprogrammed blocks remain;

b. replacing superseded data with updated data by ignoring blocks having superseded data and programming the updated data into a block containing no data without erasing the superseded data; and

c. periodically and selectively erasing all blocks having superseded data;

d. directly correlating a logical address assigned to a block of superseded data to a physical address of a corresponding block of updated data.

38. The method according to claim 37 wherein the step of periodically erasing simultaneously erases all blocks having superseded data.

39. The method according to claim 38 wherein the step of periodically erasing includes the step of simultaneously loading volatile latches from a flag means indicating that a storage block has superseded data.

40. The method according to claim 39 further comprising the step of ensuring no block is subjected to more than a predetermined number of erase cycles relative to other storage blocks.

41. The method according to claim 40 further comprising reading the mass storage device, the step of reading including:

a. receiving a logical address of a data file to be read;

b. selecting an appropriate physical address which correlates to the logical address of the data file to be read; and

c. accessing the data file to be read from storage blocks corresponding to the appropriate physical address.