Microprocessor with an external command mode for diagnosis and debugging

• US 5,479,652 A
• Filed: 10/21/1994
• Issued: 12/26/1995
• Est. Priority Date: 04/27/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Modi, Nimish H., Tripp, Mike J., Dreyer, Robert S., Alpert, Donald B.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Decady, Albert
• Application Number:
  US08/327,229
• Time in Patent Office: 431 Days
• Field of Search: 371/15.1, 371/16.1, 371/19, 371/22.1, 364/265.6, 364/267.91, 395/575
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A microprocessor is disclosed herein having an external command mode for directly accessing the execution unit, responsive to externally generated commands and instructions. An external instruction path is provided, as well as a conventional processor-driven instruction path. A multiplexer is provided that selects which of the instruction paths is actually supplied to the execution unit. Using the external command mode, the user can examine and modify registers, memory, and I/O space without otherwise affecting their contents. Any instruction executable by the execution unit is executable in the external command mode. Because direct access is provided into the execution unit, there is no implicit updating that would otherwise affect the state of the processor and require saving to an alternate memory. The present invention is implemented with a conventional test access port designed in accordance with the IEEE 1149.1 boundary scan standard, with modification to include an instruction register, a data register, and control logic. The external command mode is applicable to single and multiple pipeline processors. The circuit described herein includes several selectors for selecting between the probe mode and the processor-driven mode of operation, including an external pin, an external command, and a debug exception. For ascertaining if the circuit is in the external command mode, an acknowledge pin is provided to indicate when the execution unit is ready to accept an instruction in the probe model.

Claims

1. A computer circuit for operating in a processor-driven mode responsive to a series of stored macroinstructions from a computer memory, and also for operating in an external command mode responsive to an externally supplied microinstruction and an externally supplied command, comprising:

a mode selection unit for selecting the external command mode or the processor-driven mode;

an execution unit for executing microinstructions;

a microinstruction multiplexer for providing a selected microinstruction to the execution unit;

a processor-driven instruction path including a decoder for receiving and decoding said stored macroinstructions and decoding them into microinstructions which are then supplied to a first input of the microinstruction multiplexer;

an external instruction path for supplying an externally supplied microinstruction to a second input of the microinstruction multiplexer; and

a control circuit responsive to the mode selection unit for controlling the microinstruction multiplexer to select

during processor-driven operation, a microinstruction resulting from a decoded macroinstruction from the processor-driven instruction path, and

during external command mode operation, an externally supplied microinstruction from the external instruction path.

2. The computer circuit of claim 1 wherein the processor-driven instruction path comprises a decoder that updates the macroinstruction pointer coincident with decoding a macroinstruction.

3. The computer circuit of claim 1 wherein the external instruction path comprises an instruction register coupled to the microinstruction multiplexer, said instruction register for storing an externally supplied microinstruction.

4. The computer circuit of claim 1 wherein the mode selection unit includes a run/stop pin that, when asserted, halts operation of the processor-driven instruction path.

5. The computer circuit of claim 1 wherein the mode selection unit includes control logic, responsive to an externally supplied command, for halting operation of the processor-driven instruction path.

6. The computer circuit of claim 1 wherein the mode selection unit includes a probe mode control register that includes an instruction redirect (IR) flag for halting operation of the processor-driven instruction path when a debug exception is encountered during operation of the processor-driven instruction path.

7. The computer circuit of claim 1 further comprising an acknowledge pin that provides a signal indicative of whether the processor is in the external command mode and ready to execute an externally supplied microinstruction.

8. A computer circuit including a processor, said circuit operating in a processor-driven mode wherein the circuit executes a series of macroinstructions stored in a computer memory, and also for operating in a probe mode wherein the circuit receives an external signal that may include externally supplied commands, and externally supplied probe mode microinstructions, said circuit comprising:

a mode selection unit for selecting between the processor-driven mode and the probe mode;

an access port, including

means for receiving and sending the external signal,

means for sending information to the processor and receiving information from the processor, and

control logic for controlling the interface between the port and the processor;

a probe instruction register for holding a probe mode microinstruction received in the external signal;

a probe data register for holding data;

an execution unit for executing microinstructions; and

a microinstruction multiplexer coupled to the mode selection unit that selects a microinstruction to be provided to the execution unit, said microinstruction multiplexer selecting one of inputs including an input microinstruction decoded from a macroinstruction from the processor-driven path and an input probe mode microinstruction from the probe instruction register.

9. The computer circuit of claim 8 further comprising means, responsive to an externally supplied command, for initiating execution of a microinstruction in the probe instruction register.

10. The computer circuit of claim 8 wherein the mode selection unit includes a run/stop pin that, when asserted, halts operation of the processor-driven instruction path.

11. The computer circuit of claim 8 wherein the mode selection unit includes control logic, responsive to an externally supplied command, for halting operation of the processor-driven instruction path.

12. The computer circuit of claim 8 wherein the mode selection unit includes a probe mode control register that includes an instruction redirect flag for halting operation of the processor-driven instruction path when a debug exception is encountered during operation in the processor-driven mode.

13. The computer circuit of claim 8 further comprising an acknowledge pin that provides a signal indicative of whether the processor is in the probe mode and ready to execute a microinstruction in the probe instruction register.

14. A microprocessor for selectively operating in a processor-driven mode wherein the microprocessor is responsive to a series of macroinstructions stored in a computer memory, and for operating in an external command mode wherein the microprocessor is responsive to externally supplied microinstructions, said microprocessor comprising:

means for selecting between the external command mode and the processor-driven mode;

a decoder for receiving and decoding stored macroinstructions;

an execution unit for executing microinstructions;

means for supplying an externally supplied microinstruction to the execution unit directly, thereby bypassing the decoder when the external command mode is selected; and

means for supplying one or more microinstructions from a decoded macroinstruction from the decoder to the execution unit when the processor-driven mode is selected;

updating means for implicitly updating the processor state information before supplying said decoded microinstruction to the execution unit when said processor-driven mode is selected, said processor state information including an instruction pointer; and

means for bypassing said updating means when the external command mode is selected.

15. The microprocessor of claim 14 wherein the means for executing a stored macroinstruction in the processor driven path further comprises a decoder that updates the instruction pointer before supplying the microinstructions resulting from the decoded macroinstruction to the execution unit.

16. The microprocessor of claim 14 wherein the means for supplying an externally supplied microinstruction to the execution unit includes an instruction register for storing an externally supplied microinstruction.

17. The microprocessor of claim 14 further comprising an acknowledge pin that provides a signal indicative of whether the processor is in the external command mode and ready to execute an externally supplied microinstruction.

18. An external command method of operating a microprocessor having a pipelined instruction flow through a processor-driven instruction path that implicitly updates state information, including the instruction pointer, before supplying a microinstruction to an execution unit, said external command method comprising the steps of:

providing an external instruction path coupling an external signal with the execution unit, said external instruction path bypassing the implicit updating of the processor-driven instruction path which would otherwise result from decoding a stored macroinstruction;

supplying a microinstruction through the external instruction path for execution in the execution unit, bypassing the macroinstruction decoder in the processor-driven instruction path; and

executing said microinstruction in the execution unit.

19. The method of claim 18 wherein

the external instruction path includes an instruction register;

the step of supplying the microinstruction through the external command path includes storing the microinstruction in the instruction register; and

the step of executing the microinstruction in the execution unit comprises reading the instruction register.

20. The method of claim 18 further comprising the steps of:

providing an external data path coupling the external signal with the execution unit, said external data path including a data register that can be written or read subject to the control of an external signal;

if said microinstruction instructs reading the processor state or other data from the execution unit, then storing that data in said data register and reading out the data utilizing the external signal; and

if said microinstruction instructs writing data to the execution unit, then using the external signal to store data in the data register and then reading the data register by the execution unit.

21. The method of claim 18 further comprising a step of initiating said execution step by supplying an externally supplied command to a control unit.

22. A method of operating a microprocessor including a decoder and an execution unit, comprising the steps of:

selecting a mode of executing microinstructions, said modes including a probe mode method of executing microinstructions supplied by the external path and a processor-driven mode method of executing microinstructions which resulted from the decoding of macroinstructions stored in memory;

if the processor-driven mode has been selected, then executing microinstructions comprises the steps of

fetching a macroinstruction from memory and providing it to a decoder,

decoding the macroinstruction to provide one or more microinstructions that are applied, one after the other, to an execution unit,

updating processor state information including an instruction pointer, and

executing microinstructions supplied from the decoder; and

if the probe mode has been selected, then executing microinstructions comprises the steps of

providing an externally supplied microinstruction to the execution unit, thereby bypassing the decoder and not updating the instruction pointer and other processor state information, and

executing the externally supplied microinstruction.

23. The method of claim 22 further comprising a step of asserting an acknowledge pin to indicate when the probe mode has been selected and the processor is ready to execute an externally supplied microinstruction.

24. The method of claim 22 wherein if the probe mode has been selected, then executing externally supplied microinstructions further comprises the steps of:

storing an externally supplied microinstruction in an instruction register; and

reading the instruction register to execute said stored externally supplied microinstruction.

25. The method of claim 22 further comprising the steps of:

if said externally supplied microinstruction instructs reading data from the execution unit, then storing that data in a data register and reading out the data from the data register.

26. The method of claim 22 wherein:

if said externally supplied microinstruction instructs writing data to the execution unit, then the method further comprises the steps of storing data in the data register and then reading said data in the data register into the execution unit.

27. The method of claim 22 further comprising a step of initiating said step of executing the externally supplied microinstruction by supplying an externally supplied command to a control unit.

28. The method of claim 22 wherein the step of selecting a mode of operation includes the steps of asserting an external pin, and controlling the processor-driven instruction path so that the fetching, decoding, and updating steps of the processor-driven mode are halted.

29. The method of claim 22 wherein the step of selecting a mode of operation includes the step of applying a signal to control logic that halts the fetching, decoding, and updating operations of the processor-driven mode of operation.

30. The method of claim 22 wherein the step of selecting a mode of operation includes the steps of:

setting an interrupt redirect flag in a probe mode control register;

during operation in the processor-driven mode, detecting a debug exception;

testing the interrupt redirect flag to determine if it has been set;

if the interrupt redirect flag has been set, then selecting the probe mode with control logic that halts the fetching, decoding, and updating operations of the processor-driven mode of operation.

31. A computer circuit including a processor operating in one of a processor-driven mode in which the circuit executes a series of macroinstructions stored in a computer memory and a probe mode wherein the processor receives and processes an external signal, said circuit comprising:

an external control unit that provides said external signal including an externally supplied command and probe mode instruction;

an access port coupled to said external control unit, including

a circuit for receiving and sending the external signal;

a circuit for sending information to the processor and receiving information from the processor;

control logic for controlling the interface between the access port and the processor, and

a probe instruction register for holding a probe mode microinstruction received in the external signal;

an execution unit for executing microinstructions;

a mode selection unit for selecting between the processor-driven mode and the probe mode; and

a microinstruction multiplexer that selects a microinstruction to be provided to the execution unit, said microinstruction multiplexer having inputs including a microinstruction decoded from a macroinstruction from the processor-driven path and a probe mode microinstruction from the probe instruction register, said microinstruction multiplexer coupled to the mode selection unit to select one of said inputs.

32. The computer circuit of claim 31 further comprising a probe data register for holding data coupled between said access port and said processor.

33. The computer circuit of claim 31 wherein the mode selection unit includes a run/stop pin that, when asserted, halts operation of the processor-driven instruction path.

34. The computer circuit of claim 31 wherein the mode selection unit includes control logic, responsive to an externally supplied command, for halting operation of the processor-driven instruction path.

35. The computer circuit of claim 31 wherein the mode selection unit includes a probe mode control register that includes an instruction redirect flag for halting operation of the processor-driven instruction path when a debug exception is encountered during operation in the processor-driven mode.

36. The computer circuit of claim 31 further comprising an acknowledge pin that provides a signal indicative of whether the processor is in the probe mode and ready to execute a microinstruction in the probe instruction register.