Three-dimensional multichip package

• US 5,481,133 A
• Filed: 12/29/1994
• Issued: 01/02/1996
• Est. Priority Date: 03/21/1994
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsu, Chen-Chung
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/368,144
• Time in Patent Office: 369 Days
• Field of Search: 257/686, 257/730, 257/777, 257/621, 257/774
• US Class Current: 257/621
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A multichip array package for IC devices with a master semiconductor device supporting and electrically interconnected with a stacked array of subordinate devices. The interconnection structure has a peripheral row of contact pads on the master device. The subordinate devices each have a peripheral row of contact pads that corresponds to the peripheral row on the master device. Openings are provided through the contact pads on the subordinate devices that are in registry. The holes are filled with metal which interconnects the subordinate devices with the master device.

Claims

1. A three-dimensional multichip array package having a master integrated circuit semiconductor device supporting and interconnected with a densely stacked array of subordinate integrated circuit semiconductor devices comprising:

a base semiconductor substrate provided with interconnected integrated circuit elements, an inner peripheral row of contact pads electrically connected to said circuit elements, and an outer peripheral row of terminal pads electrically connected to said contact pads, said base substrate constituting a master semiconductor device;

a plurality of subordinate semiconductor substrates, each provided with interconnected integrated circuit elements, a peripheral row of contact pads electrically connected to said circuit elements, said row of contact pads arranged in a pattern that matches the pattern of the contact pads on said master semiconductor substrate, said subordinate semiconductor substrate constituting subordinate semiconductor devices;

an insulating layer of organic material on the surfaces of said base substrate and said subordinate substrates;

central openings through each of said contact pads of said subordinate semiconductor devices;

a dielectric coating on the walls of said central openings that extend up to but not covering the edges of said contact pads;

said subordinate semiconductor devices stacked to form an array with said central openings in registry, said array of devices supported on said master semiconductor device with said central openings in registry with said contact pads of said master semiconductor device; and

an electrically conductive material within said central openings that established electrical contact between said contact pads of said subordinate semiconductor devices and said contact pads of said master semiconductor devices.

2. The array package of claim 1 wherein said electrically conductive material in said central openings is gold.

3. The array package of claim 1 wherein said layer of organic material is polyimide.

4. The array package of claim 3 wherein said polyimide layer thickness is in the range of 5 to 10 micrometers.

5. The array package of claim 1 wherein interconnected circuit elements is covered with a layer of insulating material.

6. The array package of claim 5 wherein said insulating material is silicon oxide.

7. The array package of claim 6 wherein said layer of silicon has a thickness between about 6000 to 12000 Angstroms.

8. The array package of claim 1 wherein said contact pads on said master semiconductor device are covered with a barrier metal layer and an overlying layer of gold.

9. The array package of claim 8 wherein said barrier metal layer is titanium.

10. The array package of claim 1 wherein said contact pads of said subordinate semiconductor devices are circular, with a diameter of between about 30 to 60 micrometers.

11. The array package of claim 10 wherein said central openings each have a diameter that is smaller than the diameter of said contact pads.

12. The array package of claim 1 wherein said contact pads of said subordinate semiconductor devices have a square shape.

13. The array package of claim 1 wherein said contact pads are formed of aluminum.