High speed, low power input/output circuit for a multi-chip module

• US 5,481,207 A
• Filed: 04/19/1995
• Issued: 01/02/1996
• Est. Priority Date: 03/18/1993
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: AT&T Global Network Services LLC (AT&T, Inc.), Hyundai Electronics America Incorporated (SK Hynix Inc.)
• Inventors: Crafts, Harold S.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US08/427,916
• Time in Patent Office: 258 Days
• Field of Search: 307/443, 307/451, 307/475, 307/526-527, 326/34, 326/86, 326/30
• US Class Current: 326/86
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/018585 programmable

Abstract

An I/O transceiver circuit for use on each integrated circuit of a multi-chip module that controls the threshold voltage of the receiver portion and also controls the output resistance of the transmitter portion. Control of the threshold voltage allows operation of the circuit at low voltage levels and with relative immunity from process and temperature variations. Control of the output resistance allows operation without characteristically terminated I/O lines between multi-chip modules, thereby saving power otherwise wasted in the terminating resistors. Control of the threshold voltage is achieved by means of a reference circuit. Control of the output resistance is achieved by a phase-locked-loop arrangement. Further, the I/O transceiver circuit may also have a state where it clamps noise pulses on its I/O line.

Claims

1. An input/output transceiver circuit for an integrated circuit, comprising:

a pad located on an integrated circuit substrate;

a receiving circuit connected to said pad for receiving digital circuits inputted thereon; and

a transmitting circuit connected to said pad for transmitting digital signals to said pad;

said transmitting circuit during data transmission has an output resistance that is controlled to a constant value.

2. An input/output transceiver circuit for an integrated circuit according to claim 1, further comprising means for controlling said output resistance to a constant value connected to said transmitting circuit.

3. An input/output transceiver circuit for an integrated circuit according to claim 2, wherein said output resistance controlling means includes a phase locked loop.

4. An input/output transceiver circuit for an integrated circuit according to claim 3, wherein said phase locked loop has a voltage controlled oscillator.

5. An input/output transceiver circuit for an integrated circuit according to claim 4, wherein:

said transmitting circuit has an output stage and the resistance of said transmitting circuit is substantially the resistance of said output stage;

said voltage controlled oscillator has an output stage that is substantially the same as said transmitting circuit output stage and has an output resistance that is substantially the same as said transmitting circuit resistance;

said voltage controlled oscillator output stage resistance controls a frequency of operation of said phase locked loop and said phase locked loop maintains said natural frequency by an error signal that is fed back to said voltage controlled oscillator to maintain the resistance thereof at a constant value; and

said error signal is also connected to said transmitting circuit output stage to maintain the resistance thereof at a similar constant value.

6. An input/output transceiver circuit for an integrated circuit according to claim 1, further comprising means for clamping a signal received by said pad during non-data transmission operation.

7. An input/output transceiver circuit for an integrated circuit according to claim 1, wherein said receiving circuit includes:

a series summing amplifier means having a first inverting input, a second inverting input and an output for providing a binary output voltage at said output that is a logic low if an input voltage on said first inverting input exceeds an input voltage on said second inverting input by a threshold voltage, otherwise said binary output is a logic high; and

means for providing a reference voltage connected to said first inverting input.

8. An input/output transceiver circuit according to claim 7, further comprising;

a second series summing amplifier means having a first inverting input, a second inverting input and an output for providing a binary output voltage at said output that is a logic low if an input voltage on said first inverting input exceeds an input voltage on said second inverting input by a threshold voltage, otherwise said binary output is a logic high;

said means for providing a reference voltage is also connected to said second inverting input of said second series summing amplifier means.

9. An input/output circuit according to claim 7, further comprising:

a second series summing amplifier means having a first inverting input, a second inverting input and an output for providing a binary output voltage at said output that is a logic low if an input voltage on said first inverting input exceeds an input voltage on said second inverting input by a threshold voltage, otherwise said binary output is a logic high;

said means for providing a reference voltage is connected to said first inverting input of said second series summing amplifier;

means for providing a binary complement of a logic level impressed upon an input thereof at an output thereof connected to said output of said first series summing amplifier means;

a SET-RESET flip-flop having its SET input connected to said output of said binary complement means and its RESET input connected to said output of said second series summing amplifier; and

said first inverting input of said first series summing amplifier is connected to said second inverting input of said second series summing amplifier and to an input terminal;

wherein from said input terminal to an output of said SET-RESET flip-flop form a Schmitt trigger circuit.

10. An input/output circuit according to claim 7, further comprising:

a second series summing amplifier means having a first inverting input, a second inverting input and an output for providing a binary output voltage at said output that is a logic low if an input voltage on said first inverting input exceeds an input voltage on said second inverting input by a threshold voltage, otherwise said binary output is a logic high;

a second means for providing a reference voltage is connected to said first inverting input of said second series summing amplifier;

means for providing a binary complement of a logic level impress upon an input thereof at an output thereof connected to said output of said first series summing amplifier means;

a SET-RESET flip-flop having its SET input connected to said output of said binary complement means and its RESET input connected to said output of said second series summing amplifier; and

said first inverting input of said first series summing amplifier is connected to said second inverting input of said second series summing amplifier and to an input terminal;

wherein from said input terminal to an output of said SET-RESET flip-flop form a Schmitt trigger circuit.

11. An input/output circuit according to claim 7, wherein:

said series summing amplifier means includes a first p-channel FET, connected in series with a second p-channel FET, connected in series with a first n-channel FET, connected in series with a first n-channel FET;

a gate of said first p-channel FET and a gate of said second n-channel FET are connected and together provide said second inverting input;

a gate of said second p-channel FET and a gate of said first n-channel FET are connected and together provide said first inverting input; and

said output of said series summing amplifier means is located at the series connection point between said second p-channel FET and said first n-channel FET.

12. An input/output circuit according to claim 11, wherein:

said reference voltage providing means includes;

a series summing amplifier stage having a first inverting input, a second inverting input and an output;

said series summing amplifier stage is connected between VDD and circuit ground;

a first complementary series inverter stage having an input and an output;

said input is connected to said output of said series summing amplifier stage;

a second complementary series inverter stage having an input and an output;

said input of said second complementary series inverter stage is connected to said output of said first complementary series inverter stage;

said first inverting input is connected to a reference voltage; and

said second inverting input is connected to said output of said second complementary series inverter;

wherein an output voltage at the output of said second complementary series inverter stage is caused by this reference voltage providing means to be substantially the level of the reference voltage.

13. An input/output circuit according to claim 12, wherein said reference voltage is provided by a voltage divider.

14. An input/output circuit according to claim 13 wherein said first complementary series inverter includes a p-channel FET connected in series with an n-channel FET.

15. A input/output circuit according to claim 14, wherein said second complementary series inverter includes a p-channel FET connected in series with an n-channel FET.

16. A logic transceiver circuit comprising:

a pad on an integrated circuit substrate;

means for transmitting binary signals having a nominal logic high level of 2.0 volts and a logic low level of 1.0 volts connected to said pad, said transmitting means transmits said binary signals to said pad; and

means for receiving binary signals having a nominal logic high level of 1.6 volts and nominal logic low level of 1.4 volts also connected to said pad, said receiving means receives binary signals from said pad.

17. A logic transceiver circuit according to claim 16, wherein:

said logic transceiver circuit is an input/output circuit; and

said input/output circuit dissipates less energy because of the small difference in the logic high level and the logic low level.

18. A logic transceiver according to claim 16, wherein:

said transmitting means has means for controlling an output resistance thereof.

19. A logic transceiver circuit according to claim 18, wherein said output resistance controlling means includes a phase locked loop.

20. A logic transceiver circuit according to claim 16, wherein said receiving means has a means for controlling an input threshold thereof.

21. A logic transceiver circuit, according to claim 20, wherein said input threshold controlling means includes a stable direct current voltage means.

22. A process for producing a binary integrated circuit with threshold control voltage on each data input/output transceiver circuit, comprising the steps of:

locating a reference voltage circuit that provides a reference voltage at an output thereof on an integrated circuit chip;

locating a plurality of data input circuits, each of which has a binary input that receives respective binary input voltages, a threshold control input and a binary output;

connecting said reference voltage output to each threshold control input to control a threshold voltage that defines the point at which a binary input voltage ceases to be defined as a logic zero and begins to be defined as a logic one;

locating an output resistance controlling circuit that provides a resistance controlling voltage at an output thereof on said integrated circuit chip;

locating a plurality of data output circuits, each of which has a binary output that transmits respective binary output voltages and a resistance control input; and

connecting said resistance controlling voltage output to each resistance control input to control an output resistance of each data output circuit to a substantially constant value.

23. An integrated circuit, comprising:

a plurality of I/O transceiver circuits;

a threshold voltage control circuit connected to each of said plurality of I/O transceiver circuits to control a receiving threshold voltage characteristic thereof; and

an output resistance control circuit connected to each of said plurality of I/O transceiver circuits to control an output resistance thereof to a constant value.