Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories

• US 5,481,500 A
• Filed: 07/22/1994
• Issued: 01/02/1996
• Est. Priority Date: 07/22/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reohr, William R., Chan, Yuen H., Lu, Pong-Fei
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Le, Yu A.
• Application Number:
  US08/279,366
• Time in Patent Office: 529 Days
• Field of Search: 365/203, 365/205, 365/207, 365/208, 365/189.05, 365/194, 327/50, 327/51, 327/55, 327/57
• US Class Current: 365/203
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

Claims

1. A precharged sense amplifier arrangement including

a bistable differential amplifier,

means for enabling sensing of a differential voltage by said bistable differential amplifier, said means for enabling sensing including a means for causing latching of outputs of said differential amplifier, and

means for precharging at least said means for enabling sensing and inputs of said differential amplifier in sequence, said means for precharging including means for resetting said means for causing latching of outputs of said differential amplifier.

2. A sense amplifier as recited in claim 1 wherein said means for enabling sensing includes a dual-slope circuit.

3. A sense amplifier as recited in claim 2 wherein said means for causing latching comprises a latch circuit connected to a portion of said dual-slope circuit.

4. A method of operating a memory device including at least two sense amplifiers, each of said at least two sense amplifiers including means for precharging a respective one of said sense amplifiers in response to a precharge signal, said method including the steps of

performing a read operation concurrently with said at least two sense amplifiers,

interrupting a precharge signal to at least one of said at least two sense amplifiers, and

performing a further read operation with at least another of said at least two sense amplifiers in the same cycle as said interrupting step.