Memory testing device for multiported DRAMs

• US 5,481,671 A
• Filed: 12/30/1993
• Issued: 01/02/1996
• Est. Priority Date: 02/03/1992
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation, University of Florida (State University System of Florida)
• Original Assignee: Advantest Corporation
• Inventors: Fujisaki, Kenichi
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Wright, Norman M.
• Application Number:
  US08/122,490
• Time in Patent Office: 733 Days
• Field of Search: 371/21.1, 371/21.2, 371/21.6, 371/15.1, 371/29.1, 395/575, 395/182.06, 324/266.4, 365/201
• US Class Current: 714/6.13
• CPC Class Codes: G11C 29/003 in serial memories
• CPC Class Codes: G11C 29/20 using counters or linear-feedback shift registers [LFSR]
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A failure analysis memory (7) having main and sub failure analysis memories (7a, 7b) has two counters (C1, C2), a multiplexer (MUX), two registers (RG1, RG2)and a comparator 14. A value corresponding to the size of a column address of a memory under test (2) is set in the register (RG1) and a stop address is set in the register (RG2). Each time a SAM part (2b) of the memory under test sequentially outputs data in an address area specified by a transfer row address and a start address, one of the counters is incremented on a one-by-one basis from a start address set therein, and its count value is selected by the multiplexer (MUX) and output as a sub address signal (SA'"'"'). During this time, the other counter in the non-counting state loads therein a main address specifying data that a RAM part 2a transfers next. When the memory under test operates in a simple read/transfer mode or a split read/transfer mode, a column address in the output from the multiplexer (MUX) is compared by the comparator (14) with the value set in the register (RG1). When the memory under test operates in a stop control split read/transfer mode the column address is compared with the value set in the register (RG2). When coincidence is detected by the comparator (14), a controller (12) switches the counting and non-counting states of the counters (C1, C2).

Claims

1. A memory testing device for testing a memory device having a random access memory (RAM) part and a serial or sequential access memory (SAM) part, comprising:

timing generator means for generating and providing a timing signal;

a main pattern generating part, receiving said timing signal from said timing generator means, for applying a test pattern, a control signal and a main address signal to the RAM part of the memory device under test and outputting an expected pattern;

a sub pattern generating part, receiving said timing signal from said timing generator means, for applying a test pattern and a clock signal to the SAM part of the memory device under test and outputting an expected pattern;

the SAM part having data corresponding to said main address signal transferred from the RAM part and stored therein;

a main logical comparison part, receiving the test pattern read out of the RAM part and the expected pattern supplied from said main pattern generating part, for comparing both the test pattern and the expected pattern with each other and generating a main failure signal when a disagreement between both the test pattern and the expected pattern is detected by said main logical comparison part;

a sub logical comparison part, receiving the test pattern read out of the SAM part and the expected pattern output from said sub pattern generating part, for comparing both the test pattern and the expected pattern with each other and generating a sub failure signal when a disagreement between both the test pattern and the expected pattern is detected by said sub logical comparison part;

a failure analysis memory comprising;

a main failure analysis memory having the same storage capacity as that of the RAM part; and

a sub failure analysis memory having the same storage capacity as that of the RAM part, said main failure signal output from said main logical comparison part being written into said main failure analysis memory, said sub failure signal output from said sub logical comparison part being written into said sub failure analysis memory; and

a sub address generator provided in said failure analysis memory for generating a sub address signal that is applied to said sub failure analysis memory, said sub address generator comprising;

a plurality of counters;

a multiplexer for selecting one of said plurality of counters which is in a counting state and outputting the count value of said selected counter as a sub address signal that is input to said sub failure analysis memory;

register means for setting data of a value corresponding to a number of column addresses of said memory device under test;

comparator means for comparing at least one part of the count value of said multiplexer with at least one part of said data set in said register means and outputting a coincidence signal when coincidence is detected between them; and

control means for loading said main address signal into one of said plurality of counters in response to said coincide signal which is in a non-counting state upon each application of said main address signal thereby changing said one of said plurality of counters, into which said main address signal has been loaded, from a non-counting state thereof to a counting state thereof, incrementing said main address-loaded counter which is now in a counting state each time data corresponding to said main address signal is sequentially output from the SAM part, responding to said coincidence signal from said comparator means for stopping incrementing said one of said plurality of counters in said counting state thereby changing said one of said plurality of counters from a counting state thereof to a non-counting state thereof as well as changing said one of said plurality of counters, into which said main address signal has been loaded, from a non-counting state thereof to a counting state thereof, and incrementing said main address-loaded counter which counting state has been newly changed each time data corresponding to said main address signal is sequentially output from the SAM part.

2. The memory testing device according to claim 1, wherein said sub failure analysis memory further comprises a stop address register, receiving a stop address generated by said main pattern generating part as said main address signal, for storing said stop address therein, and wherein said comparator means is controlled by said control means to select the stop address read out of said stop address register when said SAM part is outputting data transferred thereto in a stop control split read/transfer mode, and compares said stop address with at least one part of the output from said multiplexer, and outputs said coincidence signal upon detection of coincidence therebetween.

3. The memory testing device according to claim 2, wherein said sub failure analysis memory further comprises an address selector to which said main address signal, composed of a transfer row address of said RAM part and a start address of said SAM part, is supplied from said main pattern generating part, said address selector outputting said transfer row address and said start address input thereinto in a predetermined sequence to one of said plurality of counters.

4. The memory testing device according to claim 2, wherein each of said plurality of counters is a counter which receives the set value of said register means as an enable data and is enabled for counting within a range of successive "1" bits of said enable data, said enable data containing at its least significant bit side bits "1", the number of which is equal to the number of addresses of said column address of said memory under test.

5. The memory testing device according to claim 1, wherein said sub failure analysis memory further comprises an address selector to which said main address signal, composed of a transfer row address of said RAM part and a start address of said SAM part, is supplied from said main pattern generating part, said address selector outputting said transfer row address and said start address input thereinto in a predetermined sequence to one of said plurality of counters.

6. The memory testing device according to claim 1, wherein each of said plurality of counters is a counter which receives the set value of said register means as an enable data and is enabled for counting within a range of successive "1" bits of said enable data, said enable data containing at its least significant bit side bits "1", the number of which is equal to the number of addresses of said column address of said memory under test.