Data processing apparatus having bus switches for selectively connecting buses to improve data throughput
First Claim
1. A data processing apparatus provided with an instruction storage unit, an instruction preparation unit, an instruction execution unit, and a data storage unit,said data processing apparatus comprising:
- a first bus for carrying data and addresses between the instruction storage unit and the instruction preparation unit;
a second bus for carrying data and addresses between the instruction execution unit and the data storage unit;
first switch means for selectively connecting and disconnecting said first and second buses electrically; and
control means for controlling said first switch means to connect the first and second buses when said instruction execution unit accesses said instruction storage unit and when said instruction preparation unit accesses said data storage unit, and said first switch means to disconnect the first and second buses when said instruction preparation unit accesses said instruction storage unit and when said instruction execution unit accesses said data storage unit.
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Abstract
A data processing apparatus is described, including a first bus connecting an instruction storage unit and an instruction preparation unit, a second bus connecting an instruction execution unit and a data storage unit, a bus switch selectively connecting and disconnecting the first and second buses electrically, and a control unit controlling the operation of the bus switch responding to the operations of the instruction preparation unit and the instruction execution unit. When the first and second buses are connected by the bus switch, access from the instruction preparation unit to the data storage unit and access from the instruction execution unit to the instruction storage unit can be performed. On the other hand when the buses are not connected, instruction fetch from the instruction preparation unit and data access from the instruction execution unit can be concurrently performed. Hence, data throughput on the buses can be improved and the load capacity can be reduced, which leads to heightening of the clock frequency.
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Citations
34 Claims
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1. A data processing apparatus provided with an instruction storage unit, an instruction preparation unit, an instruction execution unit, and a data storage unit,
said data processing apparatus comprising: -
a first bus for carrying data and addresses between the instruction storage unit and the instruction preparation unit; a second bus for carrying data and addresses between the instruction execution unit and the data storage unit; first switch means for selectively connecting and disconnecting said first and second buses electrically; and control means for controlling said first switch means to connect the first and second buses when said instruction execution unit accesses said instruction storage unit and when said instruction preparation unit accesses said data storage unit, and said first switch means to disconnect the first and second buses when said instruction preparation unit accesses said instruction storage unit and when said instruction execution unit accesses said data storage unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A data processing apparatus, comprising:
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an instruction storage unit for storing instructions; an instruction preparation unit for preparing instructions for execution; a first bus operatively connecting the instruction storage unit to the instruction preparation unit; an instruction execution unit for executing instructions; a data storage unit for storing data; a second bus operatively connecting the instruction execution unit to the data storage unit; means for providing a communication path between the first bus and the second bus, the communication path being provided to transmit information between the first bus and the second bus when either the instruction execution unit needs to access the instruction storage unit or the instruction preparation unit needs to access the data storage unit; and means for controlling the communication path of the first bus and second bus so that the first and second bus are connected when either the instruction execution unit accesses said instruction storage unit or the instruction preparation unit accesses said data storage unit and disconnected when either the instruction preparation unit accesses said instruction storage unit or when said instruction execution unit accesses said data storage unit.
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Specification