Method for reducing the number of bits in a binary word representing a series of addresses
First Claim
1. A method for reducing the number of bits in an initial address digital signal (AI) which represents a series of addresses, the method having at least a first step (E1) which consists successively of:
- extracting from each initial address digital signal (AI) at least one partial initial address digital signal (C1);
forming a selection address digital signal (AS) from partial initial address digital signal (C1);
extracting from each initial address digital signal (AI) a masked partial address digital signal (C3, C6) using a mask format digital signal (M1,i) selected from multiple predetermined first mask format digital signals (M1,1;
M1,2;
M1,3;
M1,4) as a function of the selection address digital signal (AS);
forming from the masked partial address digital signal (C3, C6) a first relative address digital signal (AV1); and
adding the first relative address digital signal (AV1) to a predetermined basic address digital signal (AB(M1,i)) associated with the mask format digital signal (M1,i) selected to determine the first relative address digital signal (AV1), for providing a first reduced address digital signal (AT1) with a smaller number of bits than the one in the initial address digital signal (A1); and
determining the predetermined basic address digital signal (AB(M1,i)) associated with the mask format digital signal (M1,i) by;
taking logical "0" value for the predetermined basic address digital signal (AB(M1,i) associated with the first mask format signal (M1,i) a maximum first relative address value which can be obtained using the first reduced address digital signal (AT1) incremented by one unit; and
determining a successive reduced address digital signal (AT(j)); and
successively taking for a logical value of each successive predetermined basic address digital signal (AB(Mj,k)) associated respectively with a successive mask format digital signal (Mj,k), a sum of a previous predetermined basic address digital signal (AB(Mj-1,k)) determined for a previous reduced address digital signal AT(j-1) and a maximum relative address value which can be obtained using the previous reduced address digital signal AT(j-1) incremented by one unit.
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Abstract
A method for reducing the number of bits in a binary word (AI) which represent a series of addresses, called initial addresses, having a first step (E1) which successively extracts from each initial address (AI) at least one bit (C1) with a fixed rank; forms (1) an address called the selection address (AS) from each bit or bits (C1); extracts from each initial address (AI) a series of bits (C3, C6) using a format (M1i) selected from multiple predetermined first formats (M11, M12, M13, M14), as a function of the selection address; forms (2) with this series of bits (C3, C6) a binary word called the first relative address (AV1); and adds this first relative address to an address called the predetermined basic address (AB(M1i)) associated with the format (M1i) selected to determine this first relative address so as to obtain an address called the first reduced address (AT1) having a smaller number of bits than the initial address (AI); and wherein the basic address (AB(M1 i)) associated with the one (M1i) in the first formats, consists of successively considering the first formats; taking 0 for the basic address associated with the first format considered from the first formats; and taking for the value of each basic address associated respectively with the other first formats, the sum of the last basic address determined for the previously considered first formats, and the maximum relative address value which can be obtained using the last previously considered first format incremented by one unit.
53 Citations
5 Claims
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1. A method for reducing the number of bits in an initial address digital signal (AI) which represents a series of addresses, the method having at least a first step (E1) which consists successively of:
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extracting from each initial address digital signal (AI) at least one partial initial address digital signal (C1); forming a selection address digital signal (AS) from partial initial address digital signal (C1); extracting from each initial address digital signal (AI) a masked partial address digital signal (C3, C6) using a mask format digital signal (M1,i) selected from multiple predetermined first mask format digital signals (M1,1;
M1,2;
M1,3;
M1,4) as a function of the selection address digital signal (AS);forming from the masked partial address digital signal (C3, C6) a first relative address digital signal (AV1); and adding the first relative address digital signal (AV1) to a predetermined basic address digital signal (AB(M1,i)) associated with the mask format digital signal (M1,i) selected to determine the first relative address digital signal (AV1), for providing a first reduced address digital signal (AT1) with a smaller number of bits than the one in the initial address digital signal (A1); and
determining the predetermined basic address digital signal (AB(M1,i)) associated with the mask format digital signal (M1,i) by;taking logical "0" value for the predetermined basic address digital signal (AB(M1,i) associated with the first mask format signal (M1,i) a maximum first relative address value which can be obtained using the first reduced address digital signal (AT1) incremented by one unit; and determining a successive reduced address digital signal (AT(j)); and successively taking for a logical value of each successive predetermined basic address digital signal (AB(Mj,k)) associated respectively with a successive mask format digital signal (Mj,k), a sum of a previous predetermined basic address digital signal (AB(Mj-1,k)) determined for a previous reduced address digital signal AT(j-1) and a maximum relative address value which can be obtained using the previous reduced address digital signal AT(j-1) incremented by one unit. - View Dependent Claims (2, 3, 4)
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5. A method in an asynchronous time division multiplexing telecommunication network for reducing a number of bits in an initial address digital signal (AI) which represents a series of addresses into at least one reduced address digital output signal (AT1) that forms a read-write address for a translation table, the method having at least a first step (E1) which consists successively of:
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extracting from each initial address digital signal (AI) at least one partial initial address digital signal (C1); forming a selection address digital signal (AS) from partial initial address digital signal (C1); extracting from each initial address digital signal (AI) a masked partial address digital signal (C3, C6) using a mask format digital signal (M1,i) selected from multiple predetermined first mask format digital signals (M1,1;
M1,2;
M1,3;
M1,4) as a function of the selection address digital signal (AS);forming from the masked partial address digital signal (C3, C6) a first relative address digital signal (AV1); and adding the first relative address digital signal (AV1) to a predetermined basic address digital signal (AB(M1,i)) associated with the mask format digital signal (M1,i) selected to determine the first relative address digital signal (AV1), for providing a first reduced address digital signal (AT1) with a smaller number of bits than the one in the initial address digital signal (A1); and
determining the predetermined basic address digital signal (AB(M1,i)) associated with the mask format digital signal (M1,i) by;taking logical "0" value for the predetermined basic address digital signal (AB(M1,i) associated with the first mask format signal (M1,i) a maximum first relative address value which can be obtained using the first reduced address digital signal (AT1) incremented by one unit; and determining a successive reduced address digital signal (AT(j)); and successively taking for a logical value of each successive predetermined basic address digital signal (AB(Mj,k)) associated respectively with a successive mask format digital signal (Mj,k), a sum of a previous predetermined basic address digital signal (AB(Mj-1,k)) determined for a previous reduced address digital signal AT(j-1) and a maximum relative address value which can be obtained using the previous reduced address digital signal AT(j-1) incremented by one unit.
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Specification