Dedicated processor for task I/O and memory management

• US 5,481,707 A
• Filed: 04/11/1995
• Issued: 01/02/1996
• Est. Priority Date: 05/19/1991
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Genetti, Wayne A., Thompson, Steven A., Pullin, Edward J., Wu, Gary C-F, Murphy, Philip A. Jr., Tickner, Robert H., Gunnarsson, Gunnar K.
• Primary Examiner(s): Oberley, Alvin E.
• Assistant Examiner(s): Richey, Michael T.
• Application Number:
  US08/420,329
• Time in Patent Office: 266 Days
• Field of Search: 395/275, 395/425, 395/800, 395/650, 395/700
• US Class Current: 718/102
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

A computer system performs memory to memory transfer, task scheduling and I/O request handling via a group of dedicated processors (e.g. a memory interface unit, an I/O unit, a data transfer unit, and a task control unit). The memory interface unit facilitates data interaction between the memory and the remainder of the system. The I/O unit is coupled to the memory interface unit and performs high level I/O job functions including I/O job scheduling, I/O job path selection, gathering of job statistics and device management. The data transfer unit is coupled to the memory interface unit and moves data between memory locations. The task control unit, coupled to the memory interface unit, allocates and deallocates events, maintains the status of tasks running on the system and schedules the execution of tasks. A hierarchical error reporting scheme is used by all of the processors.

Claims

1. An input/output (I/O) system including a plurality of processors, a plurality of I/O devices and a memory, said memory including a plurality of memory buffers, wherein said I/O system performs a) data transfer between said plurality of I/O devices and the memory, b) data transfer within the memory and c) task scheduling and I/O requests handling for I/O operations executed on said plurality of I/O devices, said I/O system comprising:

memory interface means

a);

for transferring a continuous block of a plurality of data values between the memory and the I/O system; and

b);

responsive to a control signal for

i) receiving said continuous block of said plurality of data values from said memory beginning at a starting address in said memory,

ii) modifying only selected data values of said continuous block of said plurality of data values received from said memory to create a continuous block of a further plurality of data values, and

iii) replacing, beginning at said starting address, said continuous block of said plurality of data values in said memory with said continuous block of said further plurality of data values;

I/O unit (IOU) means for queuing said I/O requests for said I/O operations as said I/O requests are received, selecting one of a plurality of paths within said I/O system for each of said I/O operations, collecting statistics on operation of said plurality of I/O devices and maintaining a list of said plurality of I/O devices;

data transfer unit (DTU) means for moving data among said plurality of memory buffers responsive to commands from said I/O unit means;

task control unit (TCU) means for maintaining the status of tasks on the system and for signalling each one of said plurality of processors to execute a respective one of said tasks which is in an executable state; and

channel manager unit (CMU) means for receiving data from channels associated with said plurality of I/O devices and for transferring said data to said memory interface means.

2. The system of claim 1, wherein said system is implemented on a single circuit board.

3. The system of claim 1, further coupled to a plurality of peripheral devices and further including a plurality of channel manager unit means coupled to the memory interface means for managing a plurality of data transfers between the memory and the plurality of peripheral devices.

4. The system of claim 1, further including a bus which connects the memory interface means with the I/O unit means, the data transfer unit means, the task control unit means and the channel manager unit means.

5. The system of claim 1, wherein the memory interface means is implemented with emitter coupled logic circuitry.

6. The system of claim 5 wherein the I/O unit means, the data transfer unit means, the task control unit means and the channel manager unit means are implemented with complimentary metal oxide semiconductor circuitry.

7. The system of claim 1 wherein said TCU means includes:

ready means for indicating the status of tasks running on the system wherein said ready means includes means for indicating that a task may be run on said system;

alive means for indicating the status of tasks running on the system wherein said alive means includes means for indicating that a task is running on said system; and

wait means for indicating the status of tasks running on the system wherein said wait means includes means for indicating that a task is currently unable to be executed on said system.

8. The system of claim 1 further including maintenance console means for recording error information and further including error handling means for reporting error information to said maintenance console means from said IOU means, said CMU means, said DTU means, said TCU means and said memory interface means, said error handling means comprising:

CPU reporting means for transferring error information from said CPU to said console;

IOU reporting means, coupled to said CPU reporting means for transferring error information between said IOU and said CPU;

CMU reporting means, coupled to said IOU reporting means for transferring error information between said CMU and said IOU;

DTU reporting means, coupled to said IOU reporting means for transferring error information between said DTU and said IOU;

memory interface reporting means, coupled to said CPU reporting means for transferring error information between said memory interface means and said CPU; and

TCU reporting means, coupled to said CPU reporting means for transferring error information between said TCU and said CPU.

9. The system of claim 1 further comprising:

maintenance console means for recording error information; and

error handling means for transferring error information from at least one of said IOU means, said DTU means, said TCU means, said CMU means, and said memory interface means to said maintenance console means.

10. The system of claim 1, wherein said DTU means performs block data transfers between one of said plurality of memory buffers and another one of said plurality of memory buffers.

11. The system of claim 1, wherein said I/O unit means, said data transfer unit means, said task control unit means and said channel manager unit means are each implemented in a substantially similar computer circuit.

12. A memory interface unit for transferring a plurality of data values from each of a plurality of input/output module (IOM) requestors to a memory unit, wherein said memory unit includes a continuous block of a plurality of original data values, said memory interface unit comprising:

a plurality of IOM requestors workspaces, each corresponding to a respective one of said plurality of IOM requestors;

means for transferring a plurality of data values from one of said plurality of IOM requestors to the respective one of said IOM requestor workspaces;

means for transferring memory modification information from said one of said plurality of IOM requestors to the respective one of said IOM requestor workspaces;

means for transferring a memory unit address from said one of said plurality of IOM requestors to the respective one of said IOM requestor workspaces, wherein said memory unit address is a starting address of said continuous block of said plurality of original data values in said memory unit;

means for transferring said continuous block of said plurality of original data values from said memory unit to said memory interface unit beginning at said memory unit address;

modification means, responsive to said memory modification information, for modifying only selected data values of said continuous block of said plurality of original data values which have been

a) received from said memory unit, and

b) identified by said memory modification information,

with respective ones of said plurality of data values from said one of said plurality of IOM requestors to form a continuous block of a further plurality of data values; and

means for replacing, beginning at said memory unit address, said continuous block of said plurality of original data values in said memory unit with said continuous block of said further plurality of data values.

13. The memory interface unit of claim 12, wherein said memory unit address is a logical address, further comprising:

command memory addressing (CMAD) means including means for receiving said memory unit address and for transmitting a further memory unit address to said memory unit wherein said further memory unit address is a physical address corresponding to said logical address and means for translating said logical address to said physical address;

memory interface unit controller means for selecting said IOM requestor from said plurality of IOM requestors; and

write enable store logic means for storing said data values and said memory modification information.

14. The memory interface unit of claim 12, wherein said memory interface unit implements a purgeless cache protocol and said memory interface unit does not include a cache memory.

15. The memory interface unit of claim 12, further comprising:

write enable means for transferring memory modification information from said one of said plurality of IOM requestors to said write enable storage logic means;

write full word means for transferring said plurality of original data values from said one of said plurality of IOM requestors to said corresponding IOM requestor workspace and for altering said memory modification information; and

write partial word means for transferring said plurality of original data values from said one of said plurality of IOM requestors to said corresponding IOM requestor workspace.

16. A memory interface unit according to claim 12, wherein said modification means modifies selected ones of said plurality of original data values beginning at least one byte removed from a closest word boundary of said memory unit.