Method and apparatus for providing a modular ABIOS device support layer in a computer system
First Claim
1. A personal computer system for making use of a logical memory space containing plural bounded regions, each region containing multiple address locations;
- said regions including at least a low region having discrete upper and lower boundaries, a high region having a discrete lower boundary, and an intermediate region situated between the upper boundary of said low region and the lower boundary of said high region;
said intermediate region being traditionally allocated for storing firmware information for controlling said system, said firmware information including discretely separate first and second portions of microcode;
said first portion being required by said system for completing a preliminary initialization enabling said system to handle application programs incapable of addressing said high region;
said second portion being useful by said system, after completion of said preliminary initialization, for enabling said system to handle program applications requiring access to any of said regions;
said personal computer system comprising;
a data bus;
a microprocessor electrically coupled to said data bus;
said microprocessor operating in different first and second modes characterized in that said first mode allows said microprocessor to address only said low and intermediate regions while said second mode permits said microprocessor to address any of said regions;
non-volatile memory electrically coupled to the data bus, and accessible to said microprocessor via said bus, said non-volatile memory storing said first portion of microcode for use by said microprocessor;
said non-volatile memory containing physical locations mapped into said intermediate region of said memory address space;
volatile memory electrically coupled to the data bus, and accessible to said microprocessor via said bus, said volatile memory containing physical storage locations, mapped into said low region of said address space, that are allocated for storing a linking code used by said microprocessor during a preliminary initialization of said system to initialize said system for accessing said second portion of microcode;
said linking code being invoked while said microprocessor is operating under control of said first portion of microcode during said preliminary initialization; and
,a direct access storage device electrically coupled to the data bus, and accessible to said microprocessor via said bus, said direct access storage device storing at least a part of said second portion of microcode, said second portion of microcode stored in said direct access storage device including a plurality of separately accessible modules for respectively controlling said microprocessor to perform a plurality of different functions, at least one of said functions requiring said microprocessor to have access to said high region;
said linking code controlling said microprocessor to successively;
load said modules, one at a time, from said direct access storage device into said volatile memory, examine each loaded module for pertinence to the respective system, retain the respective loaded module if it is heeded for subsequent operations of said system, and discard the respective loaded module if it is not needed for said subsequent operations.
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Abstract
A personal computer system is disclosed which is compatible with application programs and operating system software. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, a memory controller electrically coupled to the microprocessor, the volatile memory and the non-volatile memory, and a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and the volatile memory includes a volatile operating system portion intended for use by the first portion of the operating system microcode. The memory controller regulates communications between the volatile memory, the non-volatile memory and the high speed microprocessor. The direct access storage device stores a second portion of operating system microcode which includes a plurality of modules. The modules are selectively accessed by the microprocessor as needed.
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Citations
8 Claims
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1. A personal computer system for making use of a logical memory space containing plural bounded regions, each region containing multiple address locations;
- said regions including at least a low region having discrete upper and lower boundaries, a high region having a discrete lower boundary, and an intermediate region situated between the upper boundary of said low region and the lower boundary of said high region;
said intermediate region being traditionally allocated for storing firmware information for controlling said system, said firmware information including discretely separate first and second portions of microcode;
said first portion being required by said system for completing a preliminary initialization enabling said system to handle application programs incapable of addressing said high region;
said second portion being useful by said system, after completion of said preliminary initialization, for enabling said system to handle program applications requiring access to any of said regions;
said personal computer system comprising;a data bus; a microprocessor electrically coupled to said data bus;
said microprocessor operating in different first and second modes characterized in that said first mode allows said microprocessor to address only said low and intermediate regions while said second mode permits said microprocessor to address any of said regions;non-volatile memory electrically coupled to the data bus, and accessible to said microprocessor via said bus, said non-volatile memory storing said first portion of microcode for use by said microprocessor;
said non-volatile memory containing physical locations mapped into said intermediate region of said memory address space;volatile memory electrically coupled to the data bus, and accessible to said microprocessor via said bus, said volatile memory containing physical storage locations, mapped into said low region of said address space, that are allocated for storing a linking code used by said microprocessor during a preliminary initialization of said system to initialize said system for accessing said second portion of microcode;
said linking code being invoked while said microprocessor is operating under control of said first portion of microcode during said preliminary initialization; and
,a direct access storage device electrically coupled to the data bus, and accessible to said microprocessor via said bus, said direct access storage device storing at least a part of said second portion of microcode, said second portion of microcode stored in said direct access storage device including a plurality of separately accessible modules for respectively controlling said microprocessor to perform a plurality of different functions, at least one of said functions requiring said microprocessor to have access to said high region;
said linking code controlling said microprocessor to successively;
load said modules, one at a time, from said direct access storage device into said volatile memory, examine each loaded module for pertinence to the respective system, retain the respective loaded module if it is heeded for subsequent operations of said system, and discard the respective loaded module if it is not needed for said subsequent operations. - View Dependent Claims (2, 3, 4)
- said regions including at least a low region having discrete upper and lower boundaries, a high region having a discrete lower boundary, and an intermediate region situated between the upper boundary of said low region and the lower boundary of said high region;
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5. An apparatus for loading an operational interface used in the operation of a personal computer system containing a system processor, a non-volatile memory, a volatile memory, and a direct access storage device;
- said operational interface comprising discretely separate first and second portions having different memory addressing capabilities;
said first portion including first information stored in said non-volatile memory that is used by said system processor for completing a preliminary initialization of said system, and second information required by said system processor to initialize said computer system for using said second portion;
said second portion comprising plural modules having different functions;
both said first and second portions being useful for enabling said system processor to perform applications defined by application programs;
said direct access storage device storing said plurality of modules contained in said second portion of the operational interface;
said apparatus comprising;means formed by said system processor, utilizing said first information, for performing said preliminary initialization of said system and storing said second information in a predetermined part of said volatile memory; means formed by said system processor utilizing said second information, at completion of said preliminary initialization, for loading said modules of said second portion one at a time into said volatile memory and for determining in respect to each loaded module whether the computer system thereafter will require access to the respective loaded module; and said last mentioned means acting in response to each said determination to allow for the respective loaded module to be discarded if access thereto is not required and retained if access thereto is required, whereby only said loaded modules to which access is required are retained in said volatile memory. - View Dependent Claims (6, 7, 8)
- said operational interface comprising discretely separate first and second portions having different memory addressing capabilities;
Specification