Method and apparatus for providing a modular ABIOS device support layer in a computer system

• US 5,481,709 A
• Filed: 06/22/1992
• Issued: 01/02/1996
• Est. Priority Date: 06/22/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Geisler, Douglas R., Blaschke, David E., Bolt, Mary M., Bealkowski, Richard, Schroeder, Frank J., Hillis, Robert G.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Chaki, Kakali
• Application Number:
  US07/902,330
• Time in Patent Office: 1,289 Days
• Field of Search: 395/700, 395/650, 395/500
• US Class Current: 713/1
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A personal computer system is disclosed which is compatible with application programs and operating system software. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, a memory controller electrically coupled to the microprocessor, the volatile memory and the non-volatile memory, and a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and the volatile memory includes a volatile operating system portion intended for use by the first portion of the operating system microcode. The memory controller regulates communications between the volatile memory, the non-volatile memory and the high speed microprocessor. The direct access storage device stores a second portion of operating system microcode which includes a plurality of modules. The modules are selectively accessed by the microprocessor as needed.

Claims

1. A personal computer system for making use of a logical memory space containing plural bounded regions, each region containing multiple address locations;

said regions including at least a low region having discrete upper and lower boundaries, a high region having a discrete lower boundary, and an intermediate region situated between the upper boundary of said low region and the lower boundary of said high region;

said intermediate region being traditionally allocated for storing firmware information for controlling said system, said firmware information including discretely separate first and second portions of microcode;

said first portion being required by said system for completing a preliminary initialization enabling said system to handle application programs incapable of addressing said high region;

said second portion being useful by said system, after completion of said preliminary initialization, for enabling said system to handle program applications requiring access to any of said regions;

said personal computer system comprising;

a data bus;

a microprocessor electrically coupled to said data bus;

said microprocessor operating in different first and second modes characterized in that said first mode allows said microprocessor to address only said low and intermediate regions while said second mode permits said microprocessor to address any of said regions;

non-volatile memory electrically coupled to the data bus, and accessible to said microprocessor via said bus, said non-volatile memory storing said first portion of microcode for use by said microprocessor;

said non-volatile memory containing physical locations mapped into said intermediate region of said memory address space;

volatile memory electrically coupled to the data bus, and accessible to said microprocessor via said bus, said volatile memory containing physical storage locations, mapped into said low region of said address space, that are allocated for storing a linking code used by said microprocessor during a preliminary initialization of said system to initialize said system for accessing said second portion of microcode;

said linking code being invoked while said microprocessor is operating under control of said first portion of microcode during said preliminary initialization; and

,

a direct access storage device electrically coupled to the data bus, and accessible to said microprocessor via said bus, said direct access storage device storing at least a part of said second portion of microcode, said second portion of microcode stored in said direct access storage device including a plurality of separately accessible modules for respectively controlling said microprocessor to perform a plurality of different functions, at least one of said functions requiring said microprocessor to have access to said high region;

said linking code controlling said microprocessor to successively;

load said modules, one at a time, from said direct access storage device into said volatile memory, examine each loaded module for pertinence to the respective system, retain the respective loaded module if it is heeded for subsequent operations of said system, and discard the respective loaded module if it is not needed for said subsequent operations.

2. The computer system of claim 1 wherein

said first portion of microcode includes compatibility operating system microcode required for completion of said preliminary initialization, and used by said microprocessor only when said microprocessor is operating in said first mode;

said compatibility microcode being useful for enabling said microprocessor to compatibly handle programs written exclusively for a microprocessor operating in said first mode; and

said second portion of microcode includes advanced operating system microcode to be used by said microprocessor after execution of operations defined by said linking code to provide said microprocessor with access to said regions of said address space;

said second portion of microcode being used by said microprocessor in said second mode to provide access to data stored in said low, intermediate and high regions of said address space; and

said second portion of microcode being used by said microprocessor in said first mode to provide access only to data stored in said low and intermediate regions of said address space.

3. The computer system of claim 1 wherein

said plurality of modules contained in said second portion of microcode includes an initialization and control module,

said initalization and control module being loaded into said volatile memory, when access to said second portion is first required by said system after completion of said preliminary initialization, and thereafter used by said microprocessor for determining which other modules contained in said second portion are needed for subsequent use by said computer system, and for allowing only said needed other modules to be stored in said volatile memory during subsequent operations of said system.

4. The computer system of claim 1 wherein

said plurality of modules includes function modules associated with hardware components that may and may not be contained in said system;

said function modules being stored in said volatile memory only when respective said hardware components are contained in said system, and used by said microprocessor for controlling respective hardware components that are contained in said system.

5. An apparatus for loading an operational interface used in the operation of a personal computer system containing a system processor, a non-volatile memory, a volatile memory, and a direct access storage device;

said operational interface comprising discretely separate first and second portions having different memory addressing capabilities;

said first portion including first information stored in said non-volatile memory that is used by said system processor for completing a preliminary initialization of said system, and second information required by said system processor to initialize said computer system for using said second portion;

said second portion comprising plural modules having different functions;

both said first and second portions being useful for enabling said system processor to perform applications defined by application programs;

said direct access storage device storing said plurality of modules contained in said second portion of the operational interface;

said apparatus comprising;

means formed by said system processor, utilizing said first information, for performing said preliminary initialization of said system and storing said second information in a predetermined part of said volatile memory;

means formed by said system processor utilizing said second information, at completion of said preliminary initialization, for loading said modules of said second portion one at a time into said volatile memory and for determining in respect to each loaded module whether the computer system thereafter will require access to the respective loaded module; and

said last mentioned means acting in response to each said determination to allow for the respective loaded module to be discarded if access thereto is not required and retained if access thereto is required, whereby only said loaded modules to which access is required are retained in said volatile memory.

6. The computer system of claim 5 wherein said system processor is operable in different first and second modes, with a larger range of memory addressing capability in said second mode than in said first mode, and wherein

the first portion of the operational interface includes compatibility operating system microcode used only in said first mode;

said compatibility microcode enabling said system processor to compatibly handle program applications written exclusively for said first mode; and

the second portion of the operational interface includes advanced operating system microcode useful for enabling said system processor to handle program applications written for either of said first and second modes.

7. The computer system of claim 6 wherein

said plurality of modules of said second portion includes an initialization and control module and plural other modules;

said initalization and control module being loaded into said volatile memory, when access to said second portion is first required by said system after completion of said preliminary initialization, and thereafter used by said system processor for determining which particular ones of said other modules are needed for subsequent use by said computer system, and for allowing only said particular needed ones of said other modules to be stored in said volatile memory during Subsequent operations of said system.

8. The computer system of claim 5 wherein

said plurality of modules includes function modules associated with hardware components that may and may not be contained in said system;

said function modules being retained as said loaded modules in said volatile memory only when respective said hardware components are contained in said system, and said retained function modules being used by said system processor for controlling respective hardware components that are contained in said system.