Logic program comparison method for verifying a computer program in relation to a system specification
First Claim
1. A computer-based logic program verification method comprising:
- receiving two logic programs, each having procedures with program variables, each of said program variables being of a corresponding data type;
converting said logic programs to a first and second finite state machine description respectively, each having internal states, input values and output values, comprising,determining the data types of variables of said logic programs,converting said programs to a completed form having expressions in disjunctive form,expanding procedure calls within said programs into corresponding procedure bodies,translating said programs into corresponding transition functions composed of transition function expressions;
determining from said transition functions whether there exists an equivalence between internal states, between input values, and between output values of said first and second finite state machine descriptions, and determining whether said finite state machine descriptions produce respective output values deemed equal for all respective inputs deemed equal and for all respective states deemed equal; and
outputting the result of said comparing step.
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Abstract
It is an object of the present invention to provide a logic program comparison method which makes it possible to do verification by comparing parameterized logic programs and which increases the efficiency of the verification. The keyboard 1 and the input section 4 read two logic programs. The conversion section 5 converts the logic programs into the first and second finite state machine descriptions. The comparison section 6 determines whether there exists an equivalence between the states, between input values, and between output values of the first and second descriptions, and determines whether both descriptions produce respective outputs values deemed equal for all respective inputs deemed equal, for all respective states deemed equal. The result of the comparison is output through the output section 7 and the display unit 2.
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7 Claims
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1. A computer-based logic program verification method comprising:
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receiving two logic programs, each having procedures with program variables, each of said program variables being of a corresponding data type; converting said logic programs to a first and second finite state machine description respectively, each having internal states, input values and output values, comprising, determining the data types of variables of said logic programs, converting said programs to a completed form having expressions in disjunctive form, expanding procedure calls within said programs into corresponding procedure bodies, translating said programs into corresponding transition functions composed of transition function expressions; determining from said transition functions whether there exists an equivalence between internal states, between input values, and between output values of said first and second finite state machine descriptions, and determining whether said finite state machine descriptions produce respective output values deemed equal for all respective inputs deemed equal and for all respective states deemed equal; and outputting the result of said comparing step. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification