Thin film transistor matrix device

• US 5,483,082 A
• Filed: 12/28/1993
• Issued: 01/09/1996
• Est. Priority Date: 12/28/1992
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Fujitsu Limited
• Inventors: Nonaka, Kazuo, Watanabe, Kazuhiro, Takizawa, Hideaki, Hirota, Shiro, Nasu, Yasuhiro, Majima, Teiji, Sato, Seii
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): TRAN, MINH LOAN
• Application Number:
  US08/174,030
• Time in Patent Office: 742 Days
• Field of Search: 257/72, 257/57, 257/59, 257/448, 257/292, 257/71, 359/59, 359/87, 359/88
• US Class Current: 257/59
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A thin film transistor matrix device comprises a transparent insulating substrate, a thin film transistor unit, a picture element unit, a storage capacitance unit, a gate terminal unit, and a drain terminal unit, the storage capacitance unit including a storage capacitance electrode formed on the transparent insulating substrate and formed of a metal layer of the same material as the gate electrode; a dielectric film formed on the storage capacitance electrode and formed of an insulating film common with the gate insulating film and a non-doped semiconductor layer of the same material as the semiconductor active layer; and a counter electrode formed on the dielectric film and formed of a doped semiconductor layer of the same material as the semiconductor contact layer and a metal layer of the same material as the source electrode and the drain electrode, the counter electrode being connected to the picture element electrode through a contact hole opened in a protecting film common with the passivation film. Thus, the fabrication process of the TFT matrix device can be simplified, and lower costs can be realized. Characteristic changes of the storage capacitance can be prevented, and yields and reliability can be improved.

Claims

1. A thin film transistor matrix device comprising:

a transparent insulating substrate;

a thin film transistor unit including a gate electrode formed on the transparent insulating substrate;

a semiconductor active layer formed on the gate electrode through a gate insulating film;

a source electrode and a drain electrode formed opposed to each other on the semiconductor active layer respectively through a semiconductor contact layer; and

a passivation film covering the source electrode and the drain electrode;

a picture element unit including a picture element electrode formed in connection with the source electrode of the thin film transistor unit; and

a storage capacitance unit connected to the picture element electrode of the picture element unit,

the storage capacitance unit including a storage capacitance electrode formed on the transparent insulating substrate and formed of a metal layer of the same material as the gate electrode;

a dielectric film formed on the storage capacitance electrode and formed of an insulating film common with the gate insulating film and a non-doped semiconductor layer of the same material as the semiconductor active layer; and

a counter electrode formed on the dielectric film and formed of a doped semiconductor layer of the same material as the semiconductor contact layer and a metal layer of the same material as the source electrode and the drain electrode, the counter electrode being connected to the picture element electrode.

2. A thin film transistor matrix device according to claim 1, wherein

the counter electrode is connected to the picture element electrode through a contact hole opened in a protecting film common with the passivation film.

3. A thin film transistor matrix device according to claim 1, wherein

the semiconductor active layer is an amorphous silicon active layer.

4. A thin film transistor matrix device comprising:

a transparent insulating substrate;

a thin film transistor unit including a gate electrode formed on the transparent insulating substrate;

a semiconductor active layer formed on the gate electrode through a gate insulating film;

a source electrode and a drain electrode formed opposed to each other on the semiconductor active layer through a semiconductor contact layer; and

a protecting film covering the source electrode and the drain electrode;

a picture element unit including a picture element electrode formed in connection with the source electrode of the thin film transistor unit;

a storage capacitance, unit connected to the picture dement electrode of the picture element unit;

a gate terminal unit connected to the gate electrode of the thin film transistor unit through a gate bus line; and

a drain terminal unit connected to the drain electrode of the thin film transistor unit through a drain bus line,

the gate terminal unit including a gate terminal lower electrode formed on the transparent insulating substrate and formed of a metal layer common with the gate electrode;

and a gate terminal upper electrode formed on the gate terminal lower electrode through a contact hole in an insulating film common with the gate insulating film and a contact hole in the protecting film the gate terminal upper electrode being formed of a transparent conducting film of the same material as the picture element electrode, the contact hole in the insulating film and the contact hole in the protecting film being substantially aligned.

5. A thin film transistor matrix device according to claim 4, wherein

the semiconductor active layer is an amorphous silicon active layer.

6. A thin film transistor matrix device comprising:

a transparent insulating substrate;

a thin film transistor unit including a gate electrode formed on the transparent insulating substrate;

a semiconductor active layer formed on the gate electrode through a gate insulating film;

a source electrode and a drain electrode formed opposed to each other on the semiconductor active layer through a semiconductor contact layer; and

a protecting film covering the source electrode and the drain electrode;

a picture element unit including a picture element electrode formed in connection with the source electrode of the thin film transistor unit;

a storage capacitance unit connected to the picture element electrode of the picture element unit;

a gate terminal unit connected to the gate electrode of the thin film transistor unit through a gate bus line; and

a drain terminal unit connected to the drain electrode of the thin film transistor unit through a drain bus line,

the gate terminal unit including a gate terminal lower electrode formed on the transparent insulating substrate arid formed of a metal layer common with the gate electrode; and

a gate terminal upper electrode formed on the gate terminal lower electrode through a contact hole in an insulating film common with the gate insulating film and a contact hole in the protecting film, the gate terminal upper electrode being formed of a transparent conducting film of the same material as the picture element electrode, the protecting film and the insulating film being in contact in the vicinity of the contact hole in the insulating film and in the vicinity of the contact hole in the protecting film.