Electrically programmable read-only memory cell
First Claim
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1. An electrically programmable read-only memory cell comprising:
- a substrate having a first conductivity type and a primary surface;
a first doped region having a second conductivity type that is opposite the first conductivity type, wherein the first doped region lies adjacent to the primary surface of the substrate;
a pillar including a semiconductor material and overlying the first doped region and extending therefrom, wherein the pillar includes;
a central region having the first conductivity type, wherein all of the central region overlies the first doped region; and
a second doped region lying on the central region, wherein the second doped region has the second conductivity type;
a first dielectric layer lying adjacent to a side of the pillar;
a spacer lying adjacent to the first dielectric layer, wherein the spacer acts as a floating gate;
a second dielectric layer lying adjacent to the spacer, wherein the second dielectric layer includes an opening that overlies the second doped region;
a conductive member that lies adjacent to the second dielectric layer; and
an interconnect that is electrically connected to the second doped region.
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Abstract
An electrically programmable read-only memory cell includes a single crystal silicon pillar having the active region of the memory cell. A memory array of the cells may be configured to act as an EPROM array, an EEPROM array, or a flash EEPROM array. A silicon spacer lies adjacent to each of the silicon pillars and acts as a floating gate for its particular memory cell. A memory cell may have a cell area that is less than one square micron. In an EPROM or a flash EEPROM array, no field isolation is required between the memory cells within the array. Processes for forming the memory cells and the memory array are disclosed.
148 Citations
22 Claims
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1. An electrically programmable read-only memory cell comprising:
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a substrate having a first conductivity type and a primary surface; a first doped region having a second conductivity type that is opposite the first conductivity type, wherein the first doped region lies adjacent to the primary surface of the substrate; a pillar including a semiconductor material and overlying the first doped region and extending therefrom, wherein the pillar includes; a central region having the first conductivity type, wherein all of the central region overlies the first doped region; and a second doped region lying on the central region, wherein the second doped region has the second conductivity type; a first dielectric layer lying adjacent to a side of the pillar; a spacer lying adjacent to the first dielectric layer, wherein the spacer acts as a floating gate; a second dielectric layer lying adjacent to the spacer, wherein the second dielectric layer includes an opening that overlies the second doped region; a conductive member that lies adjacent to the second dielectric layer; and an interconnect that is electrically connected to the second doped region. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory array that includes a first plurality of electrically programmable read-only memory cells comprising:
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a substrate having a first conductivity type and a primary surface; at least one first doped region having a second conductivity type that is opposite the first conductivity type, wherein the at least one first doped region lies adjacent to the primary surface of the substrate; pillars including a semiconductor material, wherein; all of each pillar overlies one of the at least one first doped region; the pillars include central regions having the first conductivity type; and the pillars include second doped regions lying on the central regions, wherein the second doped regions have the second conductivity type; a first dielectric layer lying adjacent to sides of the pillars; spacers lying adjacent to the first dielectric layer, wherein the spacers act as floating gates; a second dielectric layer lying adjacent to the spacers; conductive members lying adjacent to the second dielectric layer; and interconnects that are electrically connected to the second doped regions, wherein lengths of the conductive members are perpendicular to lengths of the interconnects. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. An electrically programmable read-only memory cell comprising:
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a substrate having a first conductivity type and a primary surface; a first doped region having a second conductivity type that is opposite the first conductivity type, wherein the first doped region lies adjacent to the primary surface of the substrate; a pillar including a semiconductor material and overlying the first doped region and extending therefrom, wherein the pillar includes; a central region having the first conductivity type, wherein all of the central region overlies the first doped region; and a second doped region overlying on the central region, wherein the second doped region has the second conductivity type; a first dielectric layer lying adjacent to a side of the pillar; a spacer lying adjacent to the first dielectric layer and laterally surrounding the central region, wherein the spacer acts as a floating gate; a second dielectric layer lying adjacent to the spacer; a conductive member that lies adjacent to the second dielectric layer; and an interconnect that is electrically connected to the second doped region. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A memory array that includes a first plurality of electrically programmable read-only memory cells comprising:
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a substrate having a first conductivity type and a primary surface; at least one first doped region having a second conductivity type that is opposite the first conductivity type, wherein the at least one first doped region lies adjacent to the primary surface of the substrate; pillars including a semiconductor material, wherein; all of each pillar overlies one of the at least one first doped region; the pillars include second doped regions overlying the at least one first doped region, wherein; the second doped regions have the second conductivity type; and the at least one first doped region is electrically connected to the second doped regions of a second plurality of memory cells; the second plurality of memory cells includes at least a portion of the first plurality of memory cells; and a combination of the first and second doped regions acts as a common source region for the second plurality of memory cells; the pillars include central regions lying only on the second doped regions, wherein the central regions have the first conductivity type; and the pillars include third doped regions lying on the central regions, wherein the third doped regions have the second conductivity type; a first dielectric layer lying adjacent to sides of the pillars; spacers lying adjacent to the first dielectric layer, wherein the spacers act as floating gates; a second dielectric layer lying adjacent to the spacers; conductive members lying adjacent to the second dielectric layer, wherein one of the conductive members acts as gate electrodes for a third plurality of memory cells and as a word line for the memory array; and interconnects that are electrically connected to the third doped regions, wherein; one of the interconnects is electrically connected to the third doped regions of a fourth plurality of memory cells and acts as a bit line for the memory array; and only one memory cell is common to the third and fourth pluralities of memory cells.
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Specification