Circuit for demodulating FSK signals

• US 5,483,193 A
• Filed: 03/24/1995
• Issued: 01/09/1996
• Est. Priority Date: 03/24/1995
• Status: Expired due to Fees

• Current Assignee: Visteon Global Technologies Incorporated (Visteon Corporation)
• Original Assignee: Ford Motor Company
• Inventors: Kirk, Lawrence P., Perkins, Luke A., Kennedy, John F., Laude, David P., Campbell, Scott O.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/409,397
• Time in Patent Office: 291 Days
• Field of Search: 329/300-303, 329/341-343, 360/20, 360/27, 360/28, 360/30, 360/43, 360/48, 360/51, 375/334-337, 327/48, 327/49, 340/825.31, 340/825.32
• US Class Current: 329/300
• CPC Class Codes: H04L 27/1566 using synchronous sampling

Abstract

A circuit and method of demodulating an FSK signal uses digital circuitry to convert the received signal into count values. For each reception an adaptive reference count value is determined by averaging the duration of received pulses during the preamble of the transmission. The adaptive reference count corresponds to a demodulated logic "1" or logic level "0". The counts from the coded portion of the transmission are compared to the adaptive reference count. If the count is within predetermined windows from the reference count, the count value is converted to the corresponding digital signal.

Claims

1. A circuit for demodulating an FSK signal having a first frequency with a corresponding first period and a second frequency with a corresponding second period, said FSK signal having a preamble with a period corresponding to a selected one of said first period or said second period and a coded signal portion which alternates between said first and second periods, said circuit comprising:

receiving means receiving said FSK signal;

clock means for generating a clock signal having a third frequency corresponding to a third period substantially shorter than said first period and said second period;

counter means connected to said clock means and said receiving means for generating a count corresponding to a number of third periods of said clock signal during a period of said FSK signal;

averaging means coupled to said counter means for calculating an adaptive reference count by averaging a predetermined number of counts during said preamble, said reference count representing either the high or low logic level;

comparing means for comparing said count occurring during said coded signal portion with said adaptive reference count;

output means providing a digital level output signal based whether said count is within a predetermined range from said adaptive reference count, said predetermined range corresponding to either a valid low logic or a valid high logic.

2. A circuit for demodulating FSK signals as recited in claim 1 wherein said predetermined range defines an invalid frequency.

3. A circuit for demodulating FSK signals as recited in claim 1 wherein said output means provides an overflow signal if said counter has overflowed.

4. A circuit for demodulating FSK signals as recited in claim 1 wherein said output means includes a decision-making means for changing the digital level output signal if a predetermined number of succeeding counts corresponds to a count of an opposite logic level.

5. A circuit for demodulating FSK signals as recited in claim 1 wherein said circuit further includes an amplifier and conversion means for converting said FSK signal to a square wave, both amplifier and conversion means connected to said counter means.

7. A circuit for demodulating FSK signals as recited in claim 1 wherein a new reference level is set at each transmission.

8. A circuit for demodulating FSK signals as recited in claim 1 wherein said clock means has a frequency of about 16 MHz.

9. A circuit for demodulating FSK signals as recited in claim 1 wherein said average is taken over 10 periods of said FSK signal.

10. A circuit for demodulating FSK signals as recited in claim 1 wherein said cycle of said first and second period is at least 100 times larger than said period of said clock period.

6. A circuit for demodulating FSK signals as recited in claim I wherein said circuit further includes a digital signal processing filter connected between said counting means and comparing means for filtering said count value.

11. A circuit for demodulating FSK signals having a first frequency with a corresponding first period and a second frequency with a corresponding second period, said FSK signal having a preamble with a period corresponding to said first or second period and a coded signal portion with both first and second periods, said circuit comprising:

receiving means receiving said FSK signal;

clock means for generating a clock signal having a third frequency with a third period substantially shorter than said first period and said second period;

counter means connected to said clock means and said receiving means for generating a count corresponding to a number of third periods occurring during a period of said FSK signal;

averaging means coupled to said counter means for calculating an adaptive reference count by averaging said count from a predetermined number of periods of said preamble, said reference count representing either the high or low logic level;

comparing means for comparing said count with said reference count and providing an output signal indicative of whether said count is within a first window limit from said reference or whether said count is within a second window from said reference count, said first and second windows corresponding to one of a low logic digital signal or a high logic digital signal;

output means connected to said comparing means for generating a digital level output signal if said output signal indicates said signal is within said first or second windows.

12. A circuit for demodulating FSK signals as recited in claim 11 wherein said first window around said reference count and said second window each have a predetermined width of counts as measured from said reference count.

13. A circuit for demodulating FSK signals as recited in claim 11 wherein said comparing means further provides an output signal corresponding to an invalid frequency if said count is outside said first or second window.

14. A circuit for demodulating FSK signals as recited in claim 11 wherein said comparing means further provides an output signal if said counter has overflowed.

15. A circuit for demodulating FSK signals as recited in claim 11 wherein said output means includes a decision-making means for changing the digital level output signal of a signal corresponding to one of said windows if a predetermined number of succeeding counts are within an opposite window.

16. A circuit for demodulating FSK signals as recited in claim 11 wherein said circuit further includes an amplifier and conversion means for converting said FSK signal to a square wave, both amplifier and conversion means connected to said counter means.

17. A circuit for demodulating FSK signals as recited in claim 11 wherein said circuit further includes a digital signal processing filter connected between said counting means and comparing means for filtering said count.

18. A method for demodulating an FSK signal having a first frequency with a corresponding first period and a second frequency with a corresponding second period, said FSK signal having a preamble with a period corresponding to said first period or said second period and a coded signal portion which alternates between said first and second periods, said method comprising the steps of:

receiving said FSK signal;

generating a clock signal having a clock frequency and a clock period shorter than said first period and said second period;

counting the number of clock periods in a predetermined number of periods of said preamble;

obtaining a plurality of preamble counts;

averaging said preamble counts to obtain a reference count;

counting the number of clock periods during a period of said coded signal portion to obtain a count;

comparing said count with said reference count;

providing an output signal indicative of whether said count is within a first window limit from said reference or whether said count is within a second window from said reference count, said first and second windows corresponding to one of a low logic digital signal or a high logic digital signal; and

generating a digital level output signal if said output signal indicates said signal is within said first or second windows;

19. A method for demodulating an FSK signal as recited in claim 18 further comprising the step of generating a digital output signal if said count is outside said first or second window corresponding to an invalid frequency.

20. A method for demodulating an FSK signal as recited in claim 18 further comprising the step of generating a digital output signal if said count indicates counter overflow.