Routing algorithm method for standard-cell and gate-array integrated circuit design

• US 5,483,461 A
• Filed: 06/10/1993
• Issued: 01/09/1996
• Est. Priority Date: 06/10/1993
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: ArcSys, Inc. (Synopsys Incorporated)
• Inventors: Lin, Chin-Hsen, Liao, Yuh-Zen, Chung, Lu, Lee, Kaiwin, Wuu, Stephen
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/074,961
• Time in Patent Office: 943 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/600
• US Class Current: 716/119
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

An electronic design automation tool embodiment of the present invention comprises a five step process. In a first step, for each pin-master of arbitrary shape in a cell-master a pin access direction is identified, a region in which placing a via will connect a pin to a metal layer, and cause no design rule violation to other pin-masters, is physical bounded on the surface of a chip. Such a region is defined to be a "via-region" of the pin-master. In a second step, at least one "via-spot" within each via-region is identified that violates no design rules if vias are placed at these points. In a third step, vias are placed on each cell instance according to their via-spots. In a fourth step, a "maze-routing" is done to connect the neighboring same net pins by metal-1. In a fifth step, the vias on the pins connected by the maze-router are removed, leaving only one via on a pin if the connection for a current net is not complete.

Claims

1. A computer-implemented method of providing an electronic design automation tool for the design of a chip with at least two metal interconnecting layers (metal-1 and metal-2), said chip design being introduced to a database in a computer workstation by a user in a set of top design files and extracted in exportable form by a utility package, the method comprising the steps of:

accessing said computer database for laying boundaries for a via-region on said chip for each pin-master in a plurality of pin-masters all in a cell-master, wherein placing a via connects a pin to a plurality of metal layers without causing a pre-defined design rule violation to any other pin-master;

accessing said computer database for identifying all "via-spots" within each said via-region that violates none of said design rules if vias are placed at these points, wherein a first attempt at identification inspects points along metal-2-pitch lines and half metal-2-pitch lines in said via-region, and wherein said via-spots which have a maximum number of spots on metal-2-pitch lines and half metal-2-pitch lines are preferred;

accessing said computer database for placing vias on each cell instance according to their via-spots, such that for each cell instance, a two via-spot combination associated with it'"'"'s cell-master is found where a first combination (c1) has a maximum number of via-spots (n1) on metal-2-pitch lines and a second combination (c2) has a maximum number of via-spots (n2) on half-metal-2-pitch lines, and if n1 is greater than or equal to n2, then vias are placed at said via-spots defined by c1, otherwise said cell instance is shifted, and said vias are placed at said via-spots defined by c2;

accessing said computer database for maze-routing to connect said neighboring same net pins by metal-1; and

accessing said computer database for removing said vias on said pins connected by the maze-routing, leaving only one via on a pin if a connection for a current net is not complete.

2. The method of claim 1, wherein:

accessing said computer database for the laying of boundaries step is such that for each pin-master in a cell-master, a region is extracted and a pin access direction is identified by a program in which placing a via connection to a pin and metal layers allows direct access of pins from top or bottom and cause no design rule violations to any other pin-masters, and wherein the region is physically bounded on the surface of a chip, such region being a "via-region" on a pin-master, and further, if the via region is empty for a pin-master, vertical wires that do not cause design rule violations to other pins are added at a metal-2 pitch or one-half a metal-2 pitch position and vias and are placed at the ends of the wires to allow a direct access of said pin by a router.

3. A computer-implemented design flow method for a semiconductor chip with a single-region design comprising only standard cells, the method comprising the steps of:

a. importing data including a netlist and physical cell information for said chip design into a computer database;

b. initial floor-planning of said chip design in said database;

c. setting floor-planning options of said chip design in said database;

d. placing cells on said chip design in said database;

e. routing power and ground nets on said chip design in said database;

f. global routing said netlists in said database;

g. checking the result of said routing and returning to the step of placing cells if said routing was not acceptable;

h. detail routing said netlists in said database;

i. routing between pads of said cells in said database;

j. verifying said routing in said database; and

k. exporting a resulting design for fabrication of said chip design from said database.

4. A computer-implemented design flow method for a semiconductor chip with a multiple-region design comprising only standard cells, the method comprising the steps of:

a importing data including a netlist and physical cell information into a database in a computer;

b. initial floor-planning of said chip design in said database;

c. setting floor-planning options for said chip design in said database;

d. creating a plurality of regions for said chip design in said database;

e. assigning a plurality of cells to said regions;

f. routing power and ground nets on said chip design in said database;

g. creating region pins for said chip design in said database;

h. placing a region on said chip design in said database;

i. re-routing said power and ground nets for said chip design in said database;

j. routing at least one clock net on said chip design in said database;

k. re-creating said region pins for said chip design in said database;

l. refining a current placement of regions for said chip design in said database;

m. global routing between said placed regions for said chip design in said database;

n. detail routing between said placed regions for said chip design in said database;

o. re-creating region pins for said chip design in said database;

p. placing another region for said chip design in said database;

q. re-routing said power and ground nets for said chip design in said database;

r. re-creating said region pins for said chip design in said database;

s. refining a current placement for said chip design in said database;

t. global routing between said placed regions for said chip design in said database;

u. detail routing between said placed regions for said chip design in said database;

v. checking the result of said routing and returning to the step of placing a region if said routing was not acceptable;

w. re-routing said power and ground nets for said chip design in said database;

x. re-routing said clock nets for said chip design in said database;

y. global routing between said placed regions for said chip design in said database;

z. detail routing between said placed regions for said chip design in said database;

aa. routing between a plurality of pads on said chip design in said database;

bb. verifying said routing for said chip design in said database; and

cc. exporting a resulting design for fabrication of said chip from said database.

5. The method of claim 4, further including between the steps of (g) and (h), the steps of:

global routing between said regions for said chip design in said database; and

checking the result of said routing and returning to the step of setting floor-planning options if said routing was not acceptable for said chip design in said database.

6. The method of claim 4, further including between the steps of (l) and (m), the steps of:

global routing between said regions for said chip design in said database; and

checking the result of said routing and returning to the step of setting floor-planning options if said routing was not acceptable for said chip design in said database.

7. A computer implemented design flow method for place and route on a computer workstation of a design for a semiconductor chip with a multiple-region design comprising only standard cells provided as a physical layout and netlist in a set of top design EDIF and GDSII files to said database, the method comprising the steps of processing said database for sequentially:

a. importing data including a netlist and physical cell information;

b. initial floor-planning of said chip;

c. setting floor-planning options;

d. creating a plurality of regions;

e. assigning a plurality of cells to said regions

f. routing power and ground nets on said chip;

g. creating region pins;

h. global routing between said regions;

i. checking the result of said routing and returning to the step of setting floor-planning options if said routing was not acceptable;

j. placing a region on said chip;

k. re-routing said power and ground nets;

l. routing at least one clock net on said chip;

m. re-creating said region pins;

n. refining a current placement of regions;

o. global routing between regions;

p. checking the result of said routing and returning to the step of placing a region if said routing was not acceptable;

q. global routing between said placed regions;

r. detail routing between said placed regions;

s. re-creating region pins;

t. placing another region;

u. re-routing said power and ground nets;

v. re-creating said region pins;

w. refining a current placement;

x. global routing between said placed regions;

y. detail routing between said placed regions;

z. checking the result of said routing and returning to the step of placing a region if said routing was not acceptable;

aa. re-routing said power and ground nets;

bb. re-routing said clock nets;

cc. global routing between said placed regions;

dd. detail routing between said placed regions;

ee. routing between a plurality of pads on said chip;

ff. verifying said routing; and

gg. exporting a resulting design for fabrication of said chip.

8. An electronic design automation tool for the design of a chip with at least two metal interconnecting layers (metal-1 and metal-2), that are used in a later fabrication of the chip with conventional semiconductor manufacturing techniques, comprising:

a database structure including interconnected and interrelated cell libraries, at least one technology file, cell library format files, and top design format files all related to said chip design, wherein said database resides on a computer workstation;

computer boundary means connected to the database for laying boundaries for a via-region on said chip for each pin-master in a plurality of pin-masters all in a cell-master, wherein placing a via connects a pin to a plurality of metal layers without exceeding any of a set of a pre-defined design rules included in said database to any other pin-master;

computer identification means connected to the computer boundary means for identifying all "via-spots" within each said via-region that violates none of said design rules if vias are placed at these points, wherein a first attempt at identification inspects points along metal-2-pitch lines and half metal-2-pitch lines in said via-region, and wherein said via-spots which have a maximum number of spots on metal-2-pitch lines and half metal-2-pitch lines are preferred;

computer placement means connected to the computer identification means for placing vias on each cell instance according to their via-spots, such that for each cell instance, a two via-spot combination associated with it'"'"'s cell-master is found where a first combination (c1) has a maximum number of via-spots (n1) on metal-2-pitch lines and a second combination (c2) has a maximum number of via-spots (n2) on half-metal-2-pitch lines, and if n1 is greater than or equal to n2, then vias are placed at said via-spots defined by c1, otherwise said cell instance is shifted, and said vias are placed at said via-spots defined by c2;

computer routing means connected to the computer placement means for maze-routing to connect said neighboring same net pins by metal-1; and

computer removal means connected to the computer routing means for removing said vias on said pins connected by the maze-routing, leaving only one via on a pin if a connection for a current net is not complete.

9. The tool of claim 8, wherein:

the computer boundary means is such that for each pin-master in a cell-master, a region is extracted and a pin access direction is identified by a program in which placing a via connection to a pin and metal layers allows direct access of pins from top or bottom and cause no design rule violations to any other pin-masters, and wherein the region is physically bounded on the surface of a chip, such region being a "via-region" on a pin-master, and further, if the via region is empty for a pin-master, vertical wires that do not cause design rule violations to other pins are added at a metal-2 pitch or one-half a metal-2 pitch position and vias and are placed at the ends of the wires to allow a direct access of said pin by a router.

10. A design tool for creating a semiconductor chip with a single-region design comprising only standard cells, comprising:

a database structure including interconnected and interrelated cell libraries, at least one technology file, cell library format files, and top design format files all related to said chip design, wherein said database resides on a computer workstation with interconnected computer-implemented processes for sequentially;

a. importing data including a netlist and physical cell information;

b. initial floor-planning of said chip;

c. setting floor-planning options;

d. placing cells on said chip;

e. routing power and ground nets on said chip;

f. global routing said netlists;

g. checking the result of said routing and returning to the step of placing cells if said routing was not acceptable;

h. detail routing said netlists;

i. routing between pads of said cells;

j. verifying said routing; and

k. exporting a resulting design for fabrication of said chip back to a file in said database for read out by a user.

11. A design tool for creating a semiconductor chip with a multiple-region design comprising only standard cells, comprising:

a database structure including interconnected and interrelated cell libraries, at least one technology file, cell library format files, and top design format files all related to said chip design, wherein said database resides on a computer workstation with interconnected computer-implemented processes for sequentially;

a. importing data including a netlist and physical cell information;

b. initial floor-planning of said chip;

c. setting floor-planning options;

d. creating a plurality of regions;

e. assigning a plurality of cells to said regions

f. routing power and ground nets on said chip;

g. creating region pins;

h. placing a region on said chip;

i. re-routing said power and ground nets;

j. routing at least one clock net on said chip;

k. re-creating said region pins;

l. refining a current placement of regions;

m. global routing between said placed regions;

n. detail routing between said placed regions;

o. re-creating region pins;

p. placing another region;

q. re-routing said power and ground nets;

r. re-creating said region pins;

s. refining a current placement;

t. global routing between said placed regions;

u. detail routing between said placed regions;

v. checking the result of said routing and returning to the step of placing a region if said routing was not acceptable;

w. re-routing said power and ground nets;

x. re-routing said clock nets;

y. global routing between said placed regions;

z. detail routing between said placed regions;

aa. routing between a plurality of pads on said chip;

bb. verifying said routing; and

cc. exporting a resulting design for fabrication of said chip back to a file in said database for read out by a user.

12. The tool of claim 11, further including between the interconnected computer-implemented sequential steps of (g) and (h), the interconnected computer-implemented sequential steps of:

global routing between said regions; and

checking the result of said routing and returning to the step of setting floor-planning options if said routing was not acceptable.

13. The tool of claim 12, further including between the interconnected computer-implemented sequential steps of (l) and (m), the interconnected computer-implemented sequential steps of:

global routing between said regions; and

checking the result of said routing and returning to the step of setting floor-planning options if said routing was not acceptable.

14. A design tool for creating a semiconductor chip with a multiple-region design comprising only standard cells, comprising:

a database structure including interconnected and interrelated cell libraries, at least one technology file, cell library format files, and top design format files all related to said chip design, wherein said database resides on a computer workstation with interconnected computer-implemented processes for sequentially;

a. importing data including a netlist and physical cell information;

b. initial floor-planning of said chip;

c. setting floor-planning options;

d. creating a plurality of regions;

e. assigning a plurality of cells to said regions;

f. routing power and ground nets on said chip;

g. creating region pins;

h. global routing between said regions;

i. checking the result of said routing and returning to the step of setting floor-planning options if said routing was not acceptable;

j. placing a region on said chip;

k. re-routing said power and ground nets;

l. routing at least one clock net on said chip;

m. re-creating said region pins;

n. refining a current placement of regions;

o. global routing between regions;

p. checking the result of said routing and returning to the step of placing a region if said routing was not acceptable;

q. global routing between said placed regions;

r. detail routing between said placed regions;

s. re-creating region pins;

t. placing another region;

u. re-routing said power and ground nets;

v. re-creating said region pins;

w. refining a current placement;

x. global routing between said placed regions;

y. detail routing between said placed regions;

z. checking the result of said routing and returning to the step of placing a region if said routing was not acceptable;

aa. re-routing said power and ground nets;

bb. re-routing said clock nets;

cc. global routing between said placed regions;

dd. detail routing between said placed regions;

ee. routing between a plurality of pads on said chip;

ff. verifying said routing; and

gg. exporting a resulting design for fabrication of said chip to said database for read out by a user.