System for managing data flow among devices by storing data and structures needed by the devices and transferring configuration information from processor to the devices

• US 5,483,640 A
• Filed: 02/26/1993
• Issued: 01/09/1996
• Est. Priority Date: 02/26/1993
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Isfeld, Mark S., Mitchell, Bruce W.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): MEKY, MOUSTAFA M
• Application Number:
  US08/023,927
• Time in Patent Office: 1,047 Days
• Field of Search: 395/200, 395/275, 395/325, 395/500, 395/600, 395/650, 370/28, 370/85.2, 370/85.13, 370/85.14, 370/94.1, 370/60
• US Class Current: 709/213
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing

Abstract

An internetwork device which manages the flow of packets of I/O data among a plurality of network interface devices includes a bus coupled to the plurality of network interface devices, a core memory storing only packets of I/O data and control structures needed by the plurality of network interface devices, and a processor including local memory isolated from the core memory storing routines and internetwork information involved in updating control structures and control fields in the packets of I/O data to direct movements of packets of I/O data among the plurality of network interface devices. A bus-memory interface is provided through which transfers of packets of I/O/data and control structures used by the plurality of network interface devices are conducted between the core memory and the bus. A processor-memory interface is provided through which transfers of data to or from control structures or control fields in packets of I/O data are conducted between the core memory and the processor. Finally, a processor-bus interface is included through which configuration information concerning control structures and I/O data buffers in the core memory are transferred between the plurality of network interface devices and the processor across the bus. The processor-bus and processor-memory interfaces include structures for decoupling processor accesses to configuration stores in the plurality network interface devices and to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.

Claims

1. An apparatus for managing data flow among a plurality of input/output devices, comprising:

a core memory storing I/O data and control structures needed by the input/output devices;

a processor, including local memory isolated from the core memory and storing control information and instructions used by routines executed by the processor managing data flow among the input/output devices;

a first memory interface responsive to the plurality of input/output devices, including means, in communication with the plurality of input/output devices and the core memory, for transferring I/O data and control data between the input/output devices in the plurality of input/output devices and the I/O data and control structures in the core memory;

a second memory interface responsive to the processor, including means in communication with the processor and the core memory, for transferring control data between control structures and I/O data in the core memory and the processor, and;

a configuration interface, coupled with the plurality of input/output devices and the processor, for transferring control and status information concerning control structures and I/O data in the core memory between the plurality of input/output devices and the processor.

2. The apparatus of claim 1, wherein the second memory interface includes a read cache for reads by the processor from the core memory.

3. The apparatus of claim 1, wherein in the second interface includes a buffer for writes from the processor to the core memory.

4. The apparatus of claim 1, wherein the second memory interface includes:

means, coupled to the processor and the core memory, for decoupling processor accesses to the core memory from contention with transfers between the core memory and the plurality of input/output devices through the first memory interface.

5. The apparatus of claim 1, wherein the core memory stores only I/O data and control structures needed by the plurality of input/output devices.

6. The apparatus of claim 1, wherein the second memory interface includes:

means, coupled to the processor, the plurality of input/output devices and the core memory, for decoupling processor accesses to the plurality of input/output devices and to the core memory from contention with transfers between the core memory and the plurality of input/output devices through the first memory interface.

7. The apparatus of claim 1, wherein the means in the first memory interface for transferring data between the plurality of input/output devices and the core memory comprises a bus coupled to the plurality of input/output devices.

8. An apparatus for managing an interface among a plurality of network interface devices coupled to respective networks communicating packets of I/O data, comprising:

a bus coupled to the plurality of network interface devices;

a core memory;

a processor including local memory storing control information and routines executed by the processor involved in moving packets of I/O data among the plurality of network interface devices;

a bus-memory interface, including means, coupled to the bus and the core memory, for transferring packets of I/O data and control data used by the plurality of network interface devices between the bus and the core memory;

a processor-memory interface, including means, coupled to the processor and the core memory, for transferring control data used by the plurality of network interface devices between the core memory and the processor, and;

a configuration interface, coupled with the bus and the processor, for transferring configuration information concerning control structures and I/O data in the core memory between the plurality of network interface devices and the processor.

9. The apparatus of claim 8, wherein the processor-memory interface includes a read cache for reads by the processor from the core memory.

10. The apparatus of claim 8, wherein in the processor-memory interface includes a buffer for writes from the processor to the core memory.

11. The apparatus of claim 8, further including:

means, coupled to the processor, the bus and the core memory, for decoupling processor accesses to configuration information in the plurality of network interface devices and to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.

12. The apparatus of claim 8, wherein the core memory stores only I/O data and control structures needed by the plurality of network interface devices.

13. The apparatus of claim 8, wherein the processor-memory interface includes:

means, coupled to the processor and the core memory, for decoupling processor accesses to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.

14. The apparatus of claim 8, wherein the processor-memory interface includes:

a read cache, coupled with the core memory, for storing words from a plurality of sequential addresses in the core memory for reads by the processor from the core memory; and

a cache manager maintaining words in the read cache with burst mode transfers from the plurality of sequential addresses in core memory.

15. The apparatus of claim 8, wherein the processor-memory interface includes:

a write buffer, coupled to the core memory, for storing words for writes from the processor to plurality of sequential addresses in the core memory; and

a buffer manager writing words from the write buffer to the core memory with burst mode transfers to the plurality of sequential addresses in the core memory.

16. An apparatus for managing an interface among a plurality of network interface devices coupled to respective networks communicating packets of I/O data, comprising:

a bus coupled to the plurality of network interface devices;

a core memory storing only packets of I/O data and control structures needed by the plurality of network interface devices;

a processor including local memory isolated from the core memory storing routines executed by the processor and internetwork control information involved in updating control structures or control fields in packets of I/O data to direct movement of packets of I/O data among the plurality of network interface devices;

a bus-memory interface, including means, coupled to the bus and the core memory, for transferring packets of I/O data and control structures used by the plurality of network interface devices between the core memory and the bus;

a processor-memory interface, including means, coupled to the processor and the core memory, for transferring data to or from control structures or control fields in packets of I/O data between the core memory and the processor; and

a processor-bus interface, including means, coupled to the processor and the bus, for transferring configuration information concerning control structures and I/O data in the core memory between the plurality of network interface devices and the processor.

17. The apparatus of claim 16, wherein the processor-memory interface includes:

means, coupled to the processor and the core memory, for decoupling processor accesses to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.

18. The apparatus of claim 17, wherein the means for decoupling includes a read cache, coupled with the core memory, for reads by the processor from the core memory.

19. The apparatus of claim 18, further including a cache manager maintaining data from a plurality of sequential addresses from the core memory in the read cache.

20. The apparatus of claim 17, wherein the means for decoupling includes a write buffer, coupled with the core memory, for writes from the processor to the core memory.

21. The apparatus of claim 17, wherein the means for decoupling includes:

a read cache, coupled with the bus and the core memory, for reads by the processor from the core memory and the bus; and

a write buffer, coupled with the core memory, for writes from the processor to the core memory.

22. The apparatus of claim 21, further including a cache manager maintaining data from a plurality of sequential addresses from the core memory in the read cache.

23. The apparatus of claim 16, further including:

means, coupled to the processor, the bus and the core memory, for decoupling processor accesses to configuration stores in the plurality of network interface devices and to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.

24. The apparatus of claim 23, wherein the means for decoupling includes a read cache, coupled with the bus and core memory, for reads by the processor from configuration stores in the plurality of network interface devices and from the core memory.

25. The apparatus of claim 24, further including a cache manager maintaining data from a plurality of sequential addresses from the core memory or configuration stores in the plurality of network interface devices in the read cache.

26. The apparatus of claim 23, wherein in the means for decoupling includes a write buffer, coupled with the bus and the core memory, for writes from the processor to configuration stores in the plurality of network interface devices and to the core memory.

27. The apparatus of claim 23, wherein the means for decoupling includes:

a read cache, coupled with the bus and core memory, for reads by the processor from configuration stores in the plurality of network interface devices and from the core memory; and

a write buffer, coupled with the bus and the core memory, for writes from the processor to configuration stores in the plurality of network interface devices and to the core memory.

28. The apparatus of claim 27, further including a cache manager maintaining data from a plurality of sequential addresses from the core memory or configuration stores in the plurality of network interface devices in the read cache.

29. The apparatus of claim 16, wherein the processor-memory interface includes:

a read cache, coupled with the core memory, for storing words from a plurality of sequential addresses in the core memory for reads by the processor from the core memory; and

a cache manager maintaining words in the read cache with burst mode transfers from the plurality of sequential addresses in the core memory.

30. The apparatus of claim 16, wherein the processor-memory interface includes:

a write buffer, coupled to the core memory, for storing words for writes from the processor to plurality of sequential addresses in the core memory; and

a buffer manager writing words from the write buffer to the core memory with burst mode transfers to the plurality of sequential addresses in the core memory.