Method for manufacturing a CMOS semiconductor device

• US 5,484,739 A
• Filed: 12/08/1994
• Issued: 01/16/1996
• Est. Priority Date: 12/17/1993
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seo, Young-woo, Shin, Jung-hyun, Lee, Yong-hee
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US08/352,248
• Time in Patent Office: 404 Days
• Field of Search: 437/34, 437/46, 437/51, 437/52, 437/48, 437/57, 437/58, 437/59, 437/162, 148/DIG. 82
• US Class Current: 438/231
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: Y10S 148/082 Ion implantation FETs/COMs

Abstract

A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation. In forming the second conductivity-type area, an additional insulating layer is formed, and using a mask pattern for exposing the second conductivity area, selectively and anisotropically etched so that the remaining insulating layer or the mask pattern for exposing the second conductivity-type area serves as an impurity-implantation preventing mask.

Claims

1. A method of manufacturing a semiconductor device including at least one first conductivity-type area and at least one second conductivity-type area, said method comprising the steps of:

forming an insulating layer on a semiconductor substrate in which portions for forming said first and second conductivity-type areas are defined;

forming a first mask pattern for exposing the portion for forming said first conductivity-type area and covering the portion for forming said second conductivity-type area;

anisotropically etching said insulating layer formed on the exposed portion according to the geometric characteristics of said semiconductor substrate;

removing said first mask pattern;

forming a first material layer for forming a connection pad layer on the overall surface of the resultant structure;

implanting a first conductivity-type impurity by using said insulating layer remaining under said first material layer as an impurity implantation preventing mask;

patterning said first material layer and forming said connection pad layer on said first conductivity-type area;

forming a second mask pattern for exposing the portion for forming said second conductivity-type area and blocking the portion for forming said first conductivity-type area; and

implanting a second conductivity-type impurity by using said second mask pattern as an impurity implantation preventing mask.

2. A method of manufacturing a semiconductor device as claimed in claim 1, further comprising, prior to said step of implanting said second conductivity-type impurity, the stop of anisotropically etching said insulating layer formed on the portion exposed by said second-mask pattern according to geometric characteristics of said semiconductor substrate.

3. A method of manufacturing a semiconductor device as claimed in claim 1, further comprising, after said step of implanting said second conductivity-type impurity, the steps of:

removing said second mask pattern; and

forming an interlevel dielectric layer having a plurality of openings for exposing the portions of said connection pad layer and second conductivity-type area on the overall surface of said resultant structure.

4. A method of manufacturing a semiconductor device as claimed in claim 1, wherein said step of forming said first material layer as the connection pad layer is a step of depositing polysilicon.

5. A method of manufacturing a semiconductor device as claimed in claim 1, further comprising, prior to said step of forming said insulating layer, the steps of:

selectively defining an active area and device isolation area on said semiconductor substrate;

forming a gate insulating layer on the resultant structure;

sequentially forming a second material layer and cap insulating layer for gate electrode on said gate insulating layer;

forming a gate-mask pattern for defining said gate electrode on the resultant structure; and

sequentially and selectively etching said cap insulating layer, second material layer and gate insulating layer by using said gate-mask pattern as an etching preventing mask,

wherein spacers are formed on the sidewalls of respective gate electrodes through said step of anisotropically etching said insulating layer.

6. A method of manufacturing a semiconductor device as claimed in claim 5, further comprising, prior to said step of forming said insulating layer, the step of doping a first conductivity-type impurity on said semiconductor substrate in which portions for forming said first and second conductivity-type areas are defined.

7. A method of manufacturing a semiconductor device including at least one first conductivity-type area and at least one second conductivity-type area, said method comprising the steps of:

forming an insulating layer on a semiconductor substrate in which portions for forming said first and second conductivity-type areas are defined;

forming a first mask pattern for exposing the portion for forming said second conductivity-type area and covering the portion for forming said first conductivity-type area;

anisotropically etching said insulating layer according to the geometric characteristics of the substructure of said layer by using said second mask pattern;

removing said first mask pattern;

implanting a second conductivity-type impurity by using said etched insulating layer as an impurity implantation preventing mask;

forming a second mask pattern for exposing the portion for forming said first conductivity-type area and covering the portion for forming said second conductivity-type area;

anisotropically etching said insulating layer formed on the exposed portion according to the geometric characteristics of said semiconductor substrate;

removing said second mask pattern;

forming a first material layer for forming a connection pad layer on the overall surface of the resultant structure;

implanting a first conductivity-type impurity by using said insulating layer left under said first material layer as an impurity implantation preventing mask; and

patterning said first material layer and forming said connection pad layer on said first conductivity-type area.

8. A method of manufacturing a semiconductor device as claimed in claim 7, further comprising, after said step of forming said connection pad layer, the step of forming an interlevel dielectric layer having a plurality of openings for exposing said connection pad layer and second conductivity-type area on the overall surface of the resultant structure.

9. A method of manufacturing a semiconductor device as claimed in claim 7, wherein said first material layer is polysilicon.

10. A method of manufacturing a semiconductor device as claimed in claim 7, further comprising, prior to said step of forming said first insulating layer, the steps of:

selectively defining an active area and device isolation area on said semiconductor substrate;

forming a gate insulating layer on the resultant structure;

sequentially forming a second material layer and cap insulating layer for gate electrode on said gate insulating layer;

forming a gate-mask pattern for defining said gate electrode on the resultant structure; and

sequentially and selectively etching said cap insulating layer, second material layer and gate insulating layer by using said gate-mask pattern as an etching preventing mask,

wherein spacers are formed on the sidewalls of respective gate electrodes through said step of anisotropically etching said insulating layer.