Symbolic routing guidance for wire networks in VLSI circuits

• US 5,485,396 A
• Filed: 06/28/1991
• Issued: 01/16/1996
• Est. Priority Date: 06/28/1991
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Brasen, Daniel R., Ashtaputre, Sunil V.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/723,109
• Time in Patent Office: 1,663 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/123
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/3947 global

Abstract

A floor-plan of component blocks of logical circuits, including the symbolic routing of major connection networks, is produced as part of the process for laying out an integrated circuit on a chip. The floor-plan is produced before performing optimized placement and routing of logical circuits within component blocks of the VLSI circuit. First, the logical circuits are apportioned into component blocks. Then, an initial lay out of the component blocks of the VLSI circuit is performed. The major connection networks are routed between the component blocks so that the major connection networks are connected to connection areas within the component blocks. The initial lay out of component blocks is adjusted as necessary in order to take into account the addition of the major connection networks. Once any needed adjustments are made, routing guidance information is generated as part of the floor plan. The routing guidance information indicates locations and sizes of the major connection networks.

Claims

1. A method for laying out logical circuits on a chip, the method comprising the steps of:

(a) laying out an initial floor-plan of component blocks of the logical circuits;

(b) routing a first set of connection networks between connection areas of the component blocks;

(c) from the routing performed in step (b), generating routing guidance information which indicates location and size of the first set of connection networks;

(d) after step (c) performing optimized placement and routing of logical circuits within the component blocks; and

,

(e) after step (c) routing a second set of connection networks between the component blocks.

2. A method as in claim 1 wherein step (b) includes making any needed adjustments to the locations of component blocks as laid out in step (a) in order to take into account the locations of the first set of connection networks as laid out in step (b).

3. A method as in claim 2 wherein the first set of connection networks include a power connection network and a ground connection network.

4. A method as in claim 3 wherein the first set of connection networks additionally include a clock connection network.

5. A method as in claim 1 wherein the first set of connection networks include a power connection network and a ground connection network.

6. A method as in claim 5 wherein the first set of connection networks additionally include a clock connection network.

7. A method as in claim 1 wherein step (b) contains the substeps of:

(b.1) performing a non-optimized placement and routing of logical circuits within the component blocks which identifies connection areas for the first set of connection networks; and

,

(b.2) performing a non-optimized global route of the first set of connection networks between the connection areas of the component blocks.

8. A method as in claim 1 wherein step (b) includes determining placement of I/O pads on the chip.

9. A method for producing a floor-plan of a VLSI circuit, the floor-plan being produced before performing optimized placement and routing of logical circuits within component blocks of the VLSI circuit, and the method comprising the steps of:

(a) apportioning the logical circuits into component blocks;

(b) performing an initial lay out of the component blocks of the VLSI circuit, the initial lay out including connection areas where a first set of connection networks are connected to the component blocks;

(b) routing the first set of connection networks between the connection areas of the component blocks;

(c) making any needed adjustments to the locations of component blocks as laid out in step (a) in order to take into account the locations of the first set of connection networks as laid out in step (b); and

,

(d) from the routing performed in step (b), generating routing guidance information which indicates location and size of the first set of connection networks.

10. A method as in claim 9 wherein the first set of connection networks include a power connection network and a ground connection network.

11. A method as in claim 10 wherein the first set of connection networks additionally include a clock connection network.

12. A method as in claim 11 wherein step (b) contains the substeps of:

(b.1) performing a non-optimized placement and routing of logical circuits within the component blocks; and

,

(b.2) performing a non-optimized global route of the first set of connection networks between the component blocks.

13. A method as in claim 9 wherein step (b) includes determining placement of I/O pads on the chip.