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Symbolic routing guidance for wire networks in VLSI circuits

  • US 5,485,396 A
  • Filed: 06/28/1991
  • Issued: 01/16/1996
  • Est. Priority Date: 06/28/1991
  • Status: Expired due to Term
First Claim
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1. A method for laying out logical circuits on a chip, the method comprising the steps of:

  • (a) laying out an initial floor-plan of component blocks of the logical circuits;

    (b) routing a first set of connection networks between connection areas of the component blocks;

    (c) from the routing performed in step (b), generating routing guidance information which indicates location and size of the first set of connection networks;

    (d) after step (c) performing optimized placement and routing of logical circuits within the component blocks; and

    ,(e) after step (c) routing a second set of connection networks between the component blocks.

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