Multiple clocked dynamic sense amplifier

• US 5,485,430 A
• Filed: 09/15/1994
• Issued: 01/16/1996
• Est. Priority Date: 12/22/1992
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Inventors: McClure, David C.
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): NGUYEN, TIEP HUU
• Application Number:
  US08/306,527
• Time in Patent Office: 488 Days
• Field of Search: 365/233, 365/190, 365/207, 365/189.05, 365/203, 365/196, 365/208, 307/530, 327/51
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

A method and circuit is provided for reading a memory array which utilizes multiple clocking signals during one read cycle to enable a dynamic sense amplifier to read data from the memory array. A dynamic sense amplifier is connected to an input line, a complementary input line, and a latch. A first equilibrating signal is input into the sense amplifier, followed thereafter by a first clocking signal. The first clocking signal enables the sense amplifier to read data on the input line and complementary input line. While the sense amplifier reads the data, the sense amplifier is isolated from the input and complementary input lines. Based upon the data read by the sense amplifier, an output state is provided for the latch. After reading the data, the sense amplifier is reconnected to the input and complementary input lines. A second clocking signal then enables the sense amplifier to read the data on the input and complementary input lines a second time, and the sense amplifier is isolated from the input and complementary input lines. The output state of the latch may or may not change based upon the data read by the sense amplifier the second time.

Claims

1. A circuit for use with a memory array, comprising:

a sense amplifier connected to an input line and a complementary input line, wherein the sense amplifier senses data on the input line and complementary input line only during a clock pulse applied to a sense amplifier clock input;

a clocking circuit connected to the sense amplifier clock input, utilized to enable said sense amplifier to read data on the input line and complementary input line by generating clock pulses, wherein said clocking circuit generates, during a single read cycle of the memory array, a first clock pulse followed after a predetermined time period by a second clock pulse, wherein the single read cycle of the memory array is the period between two consecutive equilibrations of the input line and the complementary input line; and

a latch connected to the sense amplifier, wherein the latch stores data sensed by the sense amplifier during the first and second clock pulses.

2. The circuit of claim 1, wherein the output state of the latch is determined by the sense amplifier reading the data on the input and complementary input lines as a result of the first clock pulse.

3. The circuit of claim 1, wherein the output state of the latch is determined by the sense amplifier reading the data on the input and complementary input lines as a result of the second clock pulse.

4. The circuit of claim 1, wherein the sense amplifier is isolated from the input and complementary input lines at least once during the single read cycle of the memory array.

5. The circuit of claim 1, wherein the input line is a bit line in the memory array, and the complementary input line is a complementary bit line in the memory array.

6. A method for reading data from a memory array, comprising the steps of:

applying a first equilibrating signal to a sense amplifier in preparation for a single read cycle of the memory array, wherein the sense amplifier is connected to the input line and the complementary input line;

initially equilibrating an input line and a complementary input line;

applying a first clocking signal to the sense amplifier to enable the sense amplifier to read the data on the input line and complementary input line;

isolating the sense amplifier from the input line and complementary input line when applying the first clocking signal;

reading the data on the input and complementary input lines a first time;

providing an output to a latch connected to the sense amplifier as a result of reading the data on the input line and complementary input line;

reconnecting the sense amplifier to the input and complementary input lines before applying a second clocking signal to the sense amplifier;

applying the second clocking signal to the sense amplifier to enable the sense amplifier to read the data on the input line and complementary input line a second time;

reading the data on the input line and complementary input line a second time; and

subsequently equilibrating the input line and the complementary input line, wherein the input and complementary input lines are not equilibrated between the initial equilibrating step and the subsequent equilibrating step.

7. The method of claim 6, further comprising the step of applying a second equilibrating signal to the sense amplifier before the step of reconnecting the sense amplifier to the input and complementary input lines occurs.

8. The method of claim 7, further comprising the step of isolating the sense amplifier from the input and complementary input lines when applying the second equilibrating signal to the sense amplifier.

9. The method of claim 7, further comprising the step of isolating the sense amplifier from the input and complementary input lines when applying the second clocking signal to the sense amplifier.

10. The method of claim 6, further comprising the step of isolating the sense amplifier from the input line and complementary input line when applying the second clocking signal to the sense amplifier.

11. The method of claim 6, further comprising the step of providing an output state to the latch as a result of reading the data on the input line and complementary input line a second time.

12. The method of claim 6, wherein said step of reading the data on the input and complementary input lines comprises reading the data on a BIT line and corresponding complementary BIT line in the memory array.